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| author | Hui Wang <hui.wang@canonical.com> | 2023-07-31 16:46:14 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-08-06 20:17:53 +0800 |
| commit | fcf7ff67a2aa6d8055b9b815ad8a28a5231afa1e (patch) | |
| tree | 6bec9a96d595dbc4b611b44d2301b9496b020cf2 /arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | |
| parent | aca26870217b14f6ccc5a4b5c9d16879756a5ed0 (diff) | |
arm64: dts: ls1028a: add l1 and l2 cache info
When we ran the stress-ng cache related stressors, we got the log as
below:
ubuntu@ubuntu:~$ stress-ng --l1cache 4
stress-ng: info: [656] defaulting to a 86400 second (1 day, 0.00 secs) run per stressor
stress-ng: info: [656] dispatching hogs: 4 l1cache
stress-ng: info: [657] stress-ng-l1cache: skipping stressor, cannot determine cache level 1 information from kernel
This is because the l1 and l2 cache info is missing in the devicetree,
ls1028a has dual cortex-a72 cores and has 48KB icache, 32KB dcache and
1MB l2 ucache:
- icache is 3-way set associative
- dcache is 2-way set associative
- l2cache is 16-way set associative
- line size are 64bytes
Signed-off-by: Hui Wang <hui.wang@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts')
0 files changed, 0 insertions, 0 deletions