diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2021-12-16 08:41:49 -0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-02-11 11:16:17 +0800 |
| commit | afb424b99e0f556bf1324c73570028cb56d5cadb (patch) | |
| tree | b0eda1fdcaf0b51fb3822dac0356edb8009c1ec3 /arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | |
| parent | 9a0f3b157e22eb4a5f5bddd3ba820b2bee5407b0 (diff) | |
arm64: dts: imx8mm-venice*: add PCIe support
Add PCIe support to GW71xx/GW72xx/GW73xx/GW7901/GW7902
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index d52686f4c059..1b2aaf299b24 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -9,6 +9,7 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mm.dtsi" @@ -17,6 +18,7 @@ compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; aliases { + ethernet1 = ð1; usb0 = &usbotg1; usb1 = &usbotg2; }; @@ -128,6 +130,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -547,6 +555,42 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&clk IMX8MM_CLK_DUMMY>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eth1: pcie@1,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + local-mac-address = [00 00 00 00 00 00]; + }; + }; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -737,6 +781,12 @@ >; }; + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 |