diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2022-04-29 09:13:47 -0700 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-05-05 15:00:34 +0800 |
| commit | bf198e2e919ed551794d6eec3fe52e2d1693f0eb (patch) | |
| tree | d8f1dceb26fa7b69fd48dbf482bbcf79b3808e02 /arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | |
| parent | 339c8beae89b0435610b363df378abe10a486542 (diff) | |
arm64: dts: imx8mm-venice-gw7902: fix pcie bindings
Update the pcie bindings to the correct dt bindings:
pcie_phy:
- use pcie0_refclk
- add required clock-names
pcie:
- remove pcie_phy clock as it comes from phy driver
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 1b03aa154688..f0eccc5b810d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -595,7 +595,8 @@ &pcie_phy { fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; fsl,clkreq-unsupported; - clocks = <&clk IMX8MM_CLK_DUMMY>; + clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; @@ -604,8 +605,8 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; |