diff options
| author | Frieder Schrempf <frieder.schrempf@kontron.de> | 2021-10-02 02:59:52 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-10-05 14:38:48 +0800 |
| commit | 4523be8e46beb8a0992f31f53218d3f9ec267816 (patch) | |
| tree | 894ca10a276e5478883fd054f011b2c8adf94690 /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
| parent | 01df28d8085923fb1dc3c9fcb2a7676c523c66c5 (diff) | |
arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
According to the documents, the i.MX8M-Mini features a GC320 and a
GCNanoUltra GPU core. Etnaviv detects them as:
etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653
etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341
This seems to work fine more or less without any changes to the HWDB,
which still might be needed in the future to correct some features,
etc.
[lst]: Added power domains and switched clock assignments to the
new clock defines used for the composite clocks, instead of
relying on the backwards compat defines.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d8c53ffb5fff..6009e54266f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1139,6 +1139,37 @@ status = "disabled"; }; + gpu_3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + clock-names = "reg", "bus", "core", "shader"; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; + power-domains = <&pgc_gpu>; + }; + + gpu_2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU2D_ROOT>; + clock-names = "reg", "bus", "core"; + assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; + power-domains = <&pgc_gpu>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ |