diff options
| author | Adam Ford <aford173@gmail.com> | 2023-11-27 22:54:13 -0600 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-12-06 10:16:09 +0800 |
| commit | b918ab2616115c1ea441e00b054ba8d1bb912ac8 (patch) | |
| tree | 396d5cafe895e10ec7c63f677dd6f74e7c5c1b54 /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
| parent | ff2dbdf6175408108370b4d2ac6672dd13bf6d85 (diff) | |
arm64: dts: imx8mm: Simplify mipi_dsi clocks
The device tree clock structure for the mipi_dsi is
unnecessarily redundant.
The default clock parent of IMX8MM_CLK_DSI_PHY_REF is
already IMX8MM_CLK_24M, so there is no need to set the
parent-child relationship between them. The default clock
rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are
already defined to be 266MHz and 24MHz respectively,
so there is no need to define those clock rates.
On i.MX8M[MNP] the samsung,pll-clock-frequency is not
necessary, because the driver will read it from sclk_mipi
which is also already set to 24MHz making it also
redundant.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index e76fc9fb1bf4..62b4190012cf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1153,12 +1153,8 @@ clocks = <&clk IMX8MM_CLK_DSI_CORE>, <&clk IMX8MM_CLK_DSI_PHY_REF>; clock-names = "bus_clk", "sclk_mipi"; - assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, - <&clk IMX8MM_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, - <&clk IMX8MM_CLK_24M>; - assigned-clock-rates = <266000000>, <24000000>; - samsung,pll-clock-frequency = <24000000>; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; status = "disabled"; |