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authorPeng Fan <peng.fan@nxp.com>2021-08-07 17:45:35 +0800
committerShawn Guo <shawnguo@kernel.org>2021-08-14 12:39:27 +0800
commitceec36ee0d156e87f5a49d9f33dd599df6e2e233 (patch)
tree5ca481ad07ecee928c2ddb568aa8f7c0c2e32ba4 /arch/arm64/boot/dts/freescale/imx8mm.dtsi
parentc1a6018d1839c9cb8f807dc863a50102a1a5c412 (diff)
arm64: dts: imx8mm: update pmu compatible
i.MX8MM features four Cortex-A53 cores, update the compatible to use more accurate "arm,cortex-a53-pmu" Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index ddaab25b6bdb..485175cca8de 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -192,7 +192,7 @@
};
pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;