diff options
| author | Adam Ford <aford173@gmail.com> | 2022-04-26 15:51:44 -0500 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-05-05 11:53:28 +0800 |
| commit | 5446ff1a67160ad92d9aae9530846aa54750be36 (patch) | |
| tree | 12b07cac8fa9feac717fde452f5d4410525ff70d /arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi | |
| parent | 4ce01ce36d77137cf60776b320babed89de6bd4c (diff) | |
arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3
There is a header for a DB9 serial port, but any attempts to use
hardware handshaking fail. Enable RTS and CTS pin muxing and enable
handshaking in the uart node.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 0f40b43ac091..02f37dcda7ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -175,6 +175,7 @@ pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MN_CLK_UART3>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; status = "okay"; }; @@ -258,6 +259,8 @@ fsl,pins = < MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 >; }; |