diff options
author | Marek Vasut <marex@denx.de> | 2022-12-02 17:23:52 +0100 |
---|---|---|
committer | Shawn Guo <shawnguo@kernel.org> | 2022-12-31 20:35:01 +0800 |
commit | 105b9bb84f4936a5998fcd403a4439e65a84436b (patch) | |
tree | e080ef3affaeeb55e2751a93079aa3b64a0bab24 /arch/arm64/boot/dts/freescale/imx8mn.dtsi | |
parent | 5b81a87ddd56ebdcdc7bf5430bc33872168c36f4 (diff) |
arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mn.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 5f7852620fdf..c5e6c20935c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -498,6 +498,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -585,6 +587,10 @@ reg = <0x10 4>; }; + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; |