diff options
| author | Teresa Remmet <t.remmet@phytec.de> | 2023-09-06 12:08:57 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-09-25 09:35:39 +0800 |
| commit | 4a58fcdb18187fee3d88bedaa5989dccb9aa963d (patch) | |
| tree | b599b31c0e886d2ee170fcd6920668b0f2018599 /arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | |
| parent | 3bd7fdcc359eb3cd96ce8f49965b30f321979c32 (diff) | |
arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485
Add UART2 for RS232/RS485 support.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
(Updated the node by not setting the reserved bits(BIT 0 and BIT 3)
and enabled internal pullup for RX and TX.)
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 562d4fee2011..c8640cac3edc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -177,6 +177,16 @@ status = "okay"; }; +/* RS232/RS485 */ +&uart2 { + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + /* SD-Card */ &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; @@ -298,6 +308,15 @@ >; }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 + MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 + >; + }; + pinctrl_usdhc2_pins: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 |