diff options
| author | Jonas Kuenstler <j.kuenstler@phytec.de> | 2022-02-18 13:04:58 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-02-21 14:10:07 +0800 |
| commit | 59f5ae05c18a2f4a3f0494ec814155bb44a08dd7 (patch) | |
| tree | 8c53b5c3c924809d11f67cd530725fe7151e2f8a /arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | |
| parent | b00e3e03cfa2c8a2d783076ea433e5172e0a958b (diff) | |
arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC
Set the usdhc root clock to 400MHz to be able to support
HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM.
Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index c471ab252a69..79b290a002c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -197,6 +197,8 @@ /* eMMC */ &usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |