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authorTeresa Remmet <t.remmet@phytec.de>2022-02-18 13:04:53 +0100
committerShawn Guo <shawnguo@kernel.org>2022-02-21 14:09:53 +0800
commitc173a181719e7412821a357da0dc97244bf0c52d (patch)
treeebe2a5de4d448d9922ede4d563b257764dc236d8 /arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
parent4fab14f01efab40685f0d7ef66760393258ca279 (diff)
arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
Set eMMC drive strength for USDHC3_DATA lines (200Mhz) to X4 for signal improvement. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 778f601a0119..927290990d02 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -299,14 +299,14 @@
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};