diff options
| author | Marek Vasut <marex@denx.de> | 2022-12-02 17:23:52 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-12-31 20:35:01 +0800 |
| commit | 105b9bb84f4936a5998fcd403a4439e65a84436b (patch) | |
| tree | e080ef3affaeeb55e2751a93079aa3b64a0bab24 /arch/arm64/boot/dts/freescale/imx8mp.dtsi | |
| parent | 5b81a87ddd56ebdcdc7bf5430bc33872168c36f4 (diff) | |
arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 58b466633f22..dd2df83f6f27 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -380,6 +380,8 @@ compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; }; @@ -453,6 +455,10 @@ eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; + + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ + reg = <0x264 0x10>; + }; }; anatop: clock-controller@30360000 { |