summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2022-03-23 18:37:22 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2022-03-23 18:37:22 -0700
commited4643521e6af8ab8ed1e467630a85884d2696cf (patch)
treef61d6b490f9e380068952f62b51a3f3c86562451 /arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
parentb4bc93bd76d4da32600795cd323c971f00a2e788 (diff)
parentbcea9aaa4373f2ee8ea3c758b76c479dffe85822 (diff)
Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann: "After a somewhat quiet 5.17 release, the size of the DT changes is a bit larger again. There are nine new SoC that get added, all of them related to existing platforms: - Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB - Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G tablet - Microchip Lan966 networking SoC and it evaluation board - Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus 5X and Fairphone FP3 phones - Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along with their evaluation boards - Samsung Exynos 850 phone SoC and reference board - Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone - Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived from the Samsung Exynos family. - TI K3/AM62 SoC and reference board Support for additional functionality in existing dts files is added all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91, Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and Broadcom. Samsung has a rework for its pinctrl schema that is a bit tricky and requires driver changes to be included here. A few more platforms only have smaller cleanups and DT Schema fixes, this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno. The new machines are really too many to list, but I'll do it anyway: Allwinner: - A20-Marsboard development board Amlogic: - Amediatek X96-AIR (Amlogic S905X3) - CYX A95XF3-AIR (Amlogic S905X3) - Haochuangy H96-Max (Amlogic S905X3) - Amlogic AQ222 (Amlogic S4) - OSMC Vero 4K+ (Amlogic S905D) Arm Juno: - Separate DT depending on SCMI firmware version Aspeed: - Quanta S6Q BMC (AST2600) - ASRock ROMED8HM3 (AST2500) Broadcom: - Raspberry Pi Zero 2 W Marvell MVEBU/Armada: - Ctera C200 V1 NAS (kirkwood) - Ctera C200 V2 NAS (armada-370) Mstar: - DongShanPiOne, a low-end embedded board - Miyoo Mini handheld game console NXP i.MX: - Numerous i.MX8M Mini based boards in even more variations, but none based on other SoCs this time: Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and Gateworks GW7903 Qualcomm: - Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3) - SHIFT6mq phone (Snapdragon 845) - Samsung Galaxy Book2 (Snapdragon 850) - Snapdragon 8 Gen 1 Hardware Development Kit TI OMAP: - SanCloud BeagleBone Enhanced WiFi Rockchip: - Pine64 PineNote ereader tablet (rk356x) - Bananapi-R2-Pro (rk356x) STM32: - emtrion emSBS-Argon embedded board (stm32mp157c)" * tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits) arm64: dts: n5x: drop invalid property and fix edac node name arm64: dts: fsd: Add the MCT support arm64: dts: stingray: Fix spi clock name arm64: dts: ns2: Fix spi clock name ARM: dts: rockchip: Update regulator name for PX3 ARM: dts: rockchip: Add #clock-cells value for rk805 arm64: dts: rockchip: Add #clock-cells value for rk805 arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808 arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly ARM: dts: at91: sama7g5: Add NAND support ARM: dts: at91: sama7g5: add eic node ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15 arm64: dts: lg: align pl330 node name with dtschema arm64: dts: lg: add dma-cells to pl330 node arm64: dts: juno: align pl330 node name with dtschema arm64: dts: broadcom: Fix sata nodename arm64: dts: n5x: add sdr edac support arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node dt-bindings: usb: dwc2: add disable-over-current ...
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts144
1 files changed, 142 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
index fa721a13de20..94a13cb500e6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
@@ -14,6 +14,30 @@
compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
chassis-type = "laptop";
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm2 0 10000>;
+ power-supply = <&reg_main_usb>;
+ enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ brightness-levels = <0 32 64 128 160 200 255>;
+ default-brightness-level = <6>;
+ };
+
+ panel {
+ compatible = "innolux,n125hce-gn1", "simple-panel";
+ power-supply = <&reg_main_3v3>;
+ backlight = <&backlight>;
+ no-hpd;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&edp_bridge_out>;
+ };
+ };
+ };
+
pcie1_refclk: clock-pcie1-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -42,6 +66,22 @@
vin-supply = <&reg_main_5v>;
};
+ reg_main_1v8: regulator-main-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&reg_main_3v3>;
+ };
+
+ reg_main_1v2: regulator-main-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&reg_main_5v>;
+ };
+
sound {
compatible = "fsl,imx-audio-wm8960";
audio-cpu = <&sai2>;
@@ -61,6 +101,13 @@
};
};
+&dphy {
+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
+ assigned-clock-rates = <25000000>;
+ status = "okay";
+};
+
&fec1 {
status = "okay";
};
@@ -84,6 +131,67 @@
};
};
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ edp_bridge: bridge@2c {
+ compatible = "ti,sn65dsi86";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_edp_bridge>;
+ reg = <0x2c>;
+ enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ vccio-supply = <&reg_main_1v8>;
+ vpll-supply = <&reg_main_1v8>;
+ vcca-supply = <&reg_main_1v2>;
+ vcc-supply = <&reg_main_1v2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ edp_bridge_in: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ edp_bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+};
+
+&lcdif {
+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
+ /delete-property/assigned-clock-rates;
+ status = "okay";
+};
+
+&mipi_dsi {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&edp_bridge_in>;
+ };
+ };
+ };
+};
+
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
@@ -96,6 +204,13 @@
status = "okay";
};
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+
&reg_1p8v {
vin-supply = <&reg_main_5v>;
};
@@ -169,10 +284,29 @@
};
&iomuxc {
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3
+ >;
+ };
+
+ pinctrl_edp_bridge: edpbridgegrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022
+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022
+ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022
>;
};
@@ -182,6 +316,12 @@
>;
};
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3
+ >;
+ };
+
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6