diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2023-02-15 14:18:34 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-03-14 09:03:28 +0800 |
| commit | 1601bb4538c6e04f52a00ba249250cde8a396aec (patch) | |
| tree | ddde226aa80875277567fefd5af6dface1da5134 /arch/arm64/boot/dts/freescale/imx8mq.dtsi | |
| parent | 6eabc54cdf323a87da68aef511b402daf0f6d8d4 (diff) | |
arm64: dts: Add i.MX8MQ PCIe EP support
Add i.MX8MQ PCIe EP support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 98fbba4c99a9..9f950a6ac6c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1605,6 +1605,38 @@ status = "disabled"; }; + pcie1_ep: pcie-ep@33c00000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33c00000 0x000400000>, + <0x20000000 0x08000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ |