diff options
| author | Xiaolei Wang <xiaolei.wang@windriver.com> | 2023-11-10 15:25:31 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-12-06 13:24:25 +0800 |
| commit | b37e75bddc35d4a40a4caeb9921cb95c33c3eba9 (patch) | |
| tree | 8b32e9acec338f5ca6f535daa8e99c9a938c5e20 /arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | |
| parent | 7cef7c0b1dea1e17c7913826b74403f4ab7edeb9 (diff) | |
arm64: dts: imx8qm: Add imx8qm's own pm to avoid panic during startup
Add imx8qm's own pm, otherwise the following panic will
occur during the startup process:
Kernel panic - not syncing: Asynchronous SError Interrupt
Hardware name: Freescale i.MX8QM MEK (DT)
Workqueue: events_unbound deferred_probe_work_func
Call trace:
dump_backtrace+0x98/0xf0
show_stack+0x18/0x24
dump_stack_lvl+0x60/0xac
dump_stack+0x18/0x24
panic+0x340/0x3a0
nmi_panic+0x8c/0x90
arm64_serror_panic+0x6c/0x78
do_serror+0x3c/0x78
el1h_64_error_handler+0x38/0x50
el1h_64_error+0x64/0x68
fsl_edma_chan_mux+0x98/0xdc
fsl_edma_probe+0x278/0x898
platform_probe+0x68/0xd8
really_probe+0x110/0x27c
__driver_probe_device+0x78/0x12c
driver_probe_device+0x3c/0x118
__device_attach_driver+0xb8/0xf8
bus_for_each_drv+0x84/0xe4
__device_attach+0xfc/0x18c
device_initial_probe+0x14/0x20
Fixes: e4d7a330fb7a ("arm64: dts: imx8: add edma[0..3]")
Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index 01539df335f8..8439dd6b3935 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -96,6 +96,17 @@ status = "okay"; }; +&edma3 { + power-domains = <&pd IMX_SC_R_DMA_1_CH0>, + <&pd IMX_SC_R_DMA_1_CH1>, + <&pd IMX_SC_R_DMA_1_CH2>, + <&pd IMX_SC_R_DMA_1_CH3>, + <&pd IMX_SC_R_DMA_1_CH4>, + <&pd IMX_SC_R_DMA_1_CH5>, + <&pd IMX_SC_R_DMA_1_CH6>, + <&pd IMX_SC_R_DMA_1_CH7>; +}; + &flexcan1 { fsl,clk-source = /bits/ 8 <1>; }; |