diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2023-02-08 07:56:37 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-03-07 11:15:08 +0800 |
| commit | be85831de020f3cfb6811ec64f41a70bb62374b3 (patch) | |
| tree | 175877ec8671e8b28b3d97eaa22de3207efc8dd1 /arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | |
| parent | 5e7d5b023e032c30095deca9745fe8e82491ba64 (diff) | |
arm64: dts: imx8qm: add can node in devicetree
Add CAN node for imx8qm in devicetree.
Unlike on the i.MX 8QXP where the flexcan clocks are shared between
multiple CAN instances, the i.MX 8QM has separate flexcan clock slices.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index bbe5f5ecfb92..e9b198c13b2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -16,6 +16,50 @@ "uart4_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_UART_4>; }; + + can1_lpcg: clock-controller@5ace0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ace0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; + clock-output-names = "can1_lpcg_pe_clk", + "can1_lpcg_ipg_clk", + "can1_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_1>; + }; + + can2_lpcg: clock-controller@5acf0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acf0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; + clock-output-names = "can2_lpcg_pe_clk", + "can2_lpcg_ipg_clk", + "can2_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_2>; + }; +}; + +&flexcan1 { + fsl,clk-source = /bits/ 8 <1>; +}; + +&flexcan2 { + clocks = <&can1_lpcg 1>, + <&can1_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; + fsl,clk-source = /bits/ 8 <1>; +}; + +&flexcan3 { + clocks = <&can2_lpcg 1>, + <&can2_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; + fsl,clk-source = /bits/ 8 <1>; }; &lpuart0 { |