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authorAnson Huang <Anson.Huang@nxp.com>2019-10-16 10:14:23 +0800
committerShawn Guo <shawnguo@kernel.org>2019-10-28 21:48:03 +0800
commit3944b454f7fabea3ec8310e30e023102329fc85f (patch)
tree0c51e2d613051550b0e16404b789b33fb68ad245 /arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
parentbc66392d82581fd9c863cf4e02e9b63baf0723bc (diff)
arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
usdhc's clock rate is different according to different devices connected, so clock rate assignment should be placed in board DT according to different devices connected on each usdhc port. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
index 91eef9754101..a3f8cf195974 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
@@ -133,6 +133,8 @@
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
+ assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
@@ -149,6 +151,8 @@
/* SD */
&usdhc2 {
+ assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;