diff options
| author | Daniel Baluta <daniel.baluta@nxp.com> | 2019-01-16 13:21:36 +0000 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-01-22 14:29:46 +0800 |
| commit | 179cbdb8747ca551e57dc10271eb1f540499c8cf (patch) | |
| tree | 8823ca543ba5194101199411a400e94a7f5330bd /arch/arm64/boot/dts/freescale/imx8qxp.dtsi | |
| parent | fdbcc04da246876290e11e89d987cc46c237050b (diff) | |
arm64: dts: imx8qxp: Fix MU4_INT number
MU4_INT correct number is 180, while 179 is for MU3_INT.
Fixes: 3d91ba65fecd ("arm64: dts: imx: add imx8qxp support")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index bb877cf25edc..4c3dd95ed488 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -350,7 +350,7 @@ lsio_mu4: mailbox@5d1f0000 { compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1f0000 0x10000>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <0>; status = "disabled"; }; |