diff options
| author | Chester Lin <clin@suse.com> | 2021-09-08 14:45:25 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-10-04 16:09:00 +0800 |
| commit | 994f4e42ecc0a22ebcb9bf0dfde5ea8f4312c651 (patch) | |
| tree | 9b3fa4aae2bd3ed5ea9b6a455244b5b99d823fae /arch/arm64/boot/dts/freescale/s32g2.dtsi | |
| parent | aeb78b1c05d60c1639e9ade9ff285ffc31bb3e8e (diff) | |
arm64: dts: s32g2: add serial/uart support
Add serial/uart support for NXP S32G2 based on the information provided by
NXP's CodeAurora BSP.
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/s32g2.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32g2.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 53b18671deec..59ea8a25aa4c 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,6 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC + * Copyright (c) 2017-2021 NXP */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -84,6 +85,30 @@ #size-cells = <1>; ranges = <0 0 0 0x80000000>; + uart0: serial@401c8000 { + compatible = "nxp,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401c8000 0x3000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + uart1: serial@401cc000 { + compatible = "nxp,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401cc000 0x3000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + uart2: serial@402bc000 { + compatible = "nxp,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x402bc000 0x3000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; reg = <0x50800000 0x10000>, |