diff options
| author | Pierre Gondois <pierre.gondois@arm.com> | 2022-11-07 16:57:02 +0100 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2022-11-15 03:39:03 +0000 |
| commit | 0de459a3260a58169c55e2d1acf27da5ad8b635f (patch) | |
| tree | 0f3435ab3564488400f80f82c76657dacaff51f1 /arch/arm64/boot/dts/hisilicon/hip05.dtsi | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
arm64: dts: Update cache properties for hisilicon
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon/hip05.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 7b2abd10d3d6..5b2b1bfd0d2a 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -211,18 +211,22 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; }; |