summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/hisilicon
diff options
context:
space:
mode:
authorZhen Lei <thunder.leizhen@huawei.com>2020-10-12 21:17:36 +0800
committerWei Xu <xuwei5@hisilicon.com>2020-11-24 20:06:18 +0800
commitbf69b8622b940feaf61a266e304e90722875b588 (patch)
tree6b96fdba3a82e6b6110232281394201385b1895c /arch/arm64/boot/dts/hisilicon
parent4d2b9b98e3265a464445f9bbaa6d24213845a594 (diff)
arm64: dts: hisilicon: normalize the node name of the UART devices
Change the node name of the UART devices to match "^serial(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon')
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip05.dtsi4
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06.dtsi2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index f7e3a7af4634..26caf09e9511 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -296,7 +296,7 @@
clock-frequency = <200000000>;
};
- uart0: uart@80300000 {
+ uart0: serial@80300000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80300000 0x0 0x10000>;
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
@@ -307,7 +307,7 @@
status = "disabled";
};
- uart1: uart@80310000 {
+ uart1: serial@80310000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80310000 0x0 0x10000>;
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 2d401d74a01f..7980709e21ff 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -359,7 +359,7 @@
status = "disabled";
};
- uart0: lpc-uart@2f8 {
+ uart0: serial@2f8 {
compatible = "ns16550a";
clock-frequency = <1843200>;
reg = <0x01 0x2f8 0x08>;