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authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2022-04-19 12:03:57 +0200
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2022-04-19 12:06:54 +0200
commit65b96377bf9130617ced41f317f3ec387d3e0dc3 (patch)
treef3693d46ee26e3f90b9ac35aa0e50068c6d46b76 /arch/arm64/boot/dts/hisilicon
parent3123109284176b1532874591f7c81f3837bbdc17 (diff)
arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS
The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220306111125.116455-10-krzysztof.kozlowski@canonical.com
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon')
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3660.dtsi4
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3670.dtsi4
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 8bd6d7e8a474..6b3057a09251 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -1045,8 +1045,8 @@
clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
clock-names = "ref_clk", "phy_clk";
- freq-table-hz = <0 0
- 0 0>;
+ freq-table-hz = <0 0>,
+ <0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 636c8817df7e..3125c3869c69 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -671,8 +671,8 @@
clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
clock-names = "ref_clk", "phy_clk";
- freq-table-hz = <0 0
- 0 0>;
+ freq-table-hz = <0 0>,
+ <0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";