diff options
| author | David Yang <mmyangfl@gmail.com> | 2023-05-14 20:25:33 +0800 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2023-08-03 12:37:20 +0000 |
| commit | dc8cbdd9c68d1e840aec926bee714c38f5e315a5 (patch) | |
| tree | 36807fa61bec41772e26110f55578f5c15c057c2 /arch/arm64/boot/dts/hisilicon | |
| parent | 942815c2459894fb839fd91b6beb88b1944ec242 (diff) | |
arm64: dts: hi3798cv200: Fix clocks order of sd0
"ciu" and "biu" were incorrectly swapped. Fix their order.
Signed-off-by: David Yang <mmyangfl@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index a83b9d4f172e..ed1b5a7a6067 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -302,8 +302,8 @@ compatible = "snps,dw-mshc"; reg = <0x9820000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg HISTB_SDIO0_CIU_CLK>, - <&crg HISTB_SDIO0_BIU_CLK>; + clocks = <&crg HISTB_SDIO0_BIU_CLK>, + <&crg HISTB_SDIO0_CIU_CLK>; clock-names = "biu", "ciu"; resets = <&crg 0x9c 4>; reset-names = "reset"; |