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authorOoi, Joyce <joyce.ooi@intel.com>2019-10-08 01:46:39 -0700
committerDinh Nguyen <dinguyen@kernel.org>2019-10-21 22:44:04 -0500
commitc4c8757b2d8956ae48d4d3b4acd400835c98921e (patch)
tree42bc51c373cbf6e383aafce4e1df31a1cb39648c /arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
parente683c4b078d824ba1620477efee6be6f4ed647f9 (diff)
arm64: dts: agilex: add QSPI support for Intel Agilex
This patch adds QSPI flash interface in device tree for Intel Agilex Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts')
-rw-r--r--arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts35
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index 7814a9e8eb08..866205ac7d51 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -73,3 +73,38 @@
&watchdog0 {
status = "okay";
};
+
+&qspi {
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mt25qu02g";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x034B0000>;
+ };
+
+ qspi_rootfs: partition@34B0000 {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x034B0000 0x0EB50000>;
+ };
+ };
+ };
+};