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| author | Niravkumar L Rabara <niravkumar.l.rabara@intel.com> | 2023-08-02 10:58:42 +0800 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2023-08-08 06:32:34 -0500 |
| commit | d5f0942b5066e28138476259d076e4d6c871da7d (patch) | |
| tree | 68593ece6a1c23a4fa710dec235a37f93f0b50ef /arch/arm64/boot/dts/intel | |
| parent | 2a29fe831f80f6d9187e49a272d795f3d1b54cdb (diff) | |
dt-bindings: clock: add Intel Agilex5 clock manager
Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.
Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/intel')
0 files changed, 0 insertions, 0 deletions