diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2020-12-07 14:43:01 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2021-01-04 15:40:31 -0600 |
| commit | a427485a009348f0c7a498e34788a4c5adcc7128 (patch) | |
| tree | 8f5fa7183fa63356e1cf69ce36b500d047fd5a4a /arch/arm64/boot/dts/intel | |
| parent | 62b3c680cfdc1f60a9143a1e4aabff7473629157 (diff) | |
arm64: dts: n5x: Add support for Intel's eASIC N5X platform
The Intel eASIC N5X platform shares the same register map as the Agilex
platform, thus, we can re-use the socfpga_agilex.dtsi as the base
DTSI.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/intel')
| -rw-r--r-- | arch/arm64/boot/dts/intel/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 53 |
2 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 296eceec4276..3a052540605b 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,3 +2,4 @@ dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb +dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts new file mode 100644 index 000000000000..5f56e2697fee --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021, Intel Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model = "eASIC N5X SoCDK"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&clkmgr { + compatible = "intel,easic-n5x-clkmgr"; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; |