diff options
| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-09-25 16:53:52 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-09-27 15:34:01 +0200 |
| commit | 73ae5fe8a52ff8543011e476e406f83e80a53145 (patch) | |
| tree | abca6112fb79fe3caf38c5402ad254ed3b6095a1 /arch/arm64/boot/dts/marvell/armada-7040-db.dts | |
| parent | 441fadadaebacfd5079648354b511a9f21ce9fd7 (diff) | |
arm64: dts: marvell: add NAND support on the 7040-DB board
The NAND controller used in A7K/A8K is present on the CP110 master part.
It is compatible with the pxa3xx_nand driver but requires the use of the
marvell,armada-8k-nand compatible string due to the need to first enable
the NAND controller.
Add properties to the NAND node to fit the bindings constraints of the
pxa3xx_nand driver and enable the NAND controller.
Add the 'marvell,system-controller' property to the cp110 master NAND
node with a reference to the syscon node. This is new compared to other
boards using the pxa3xx_nand driver and it is needed to be bootloader
independent and enable the NAND controller from the NAND controller
driver itself by writing in these syscon registers.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
[miquel.raynal@free-electrons.com: add NAND ready/busy MPP subnode,
change compatible string to fit the needs of the A7k/A8k SoCs and add
the system controller property]
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-7040-db.dts')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-7040-db.dts | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index 8588c6de3c8e..8f3b395c786c 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -146,6 +146,36 @@ }; }; +&cpm_nand { + /* + * SPI on CPM and NAND have common pins on this board. We can + * use only one at a time. To enable the NAND (whihch will + * disable the SPI), the "status = "okay";" line have to be + * added here. + */ + num-cs = <1>; + pinctrl-0 = <&nand_pins>, <&nand_rb>; + pinctrl-names = "default"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "Linux"; + reg = <0x200000 0xe00000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; +}; + + &cpm_spi1 { status = "okay"; |