diff options
| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-10-04 16:27:30 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-09 09:36:41 +0200 |
| commit | 1399672e48b573f6526b9ac78cfd50314f0b01a6 (patch) | |
| tree | 740410e846cf9552b86ed8c3214bfa3dfa5fe8bf /arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | |
| parent | 47cf40af64c35a69ef6a193c47768ad1bda29db2 (diff) | |
arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to
RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory
range. This shows that I/O memory has never been used/working on the
old SoCs despite the region being advertised. As PCIe I/O ranges will
not be supported in newer SoCs using CP11x co-processors, let's
simply drop them. It is not harmful in any case as PCIe device drivers
can do it all with the regular mapped memory anyway.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index d250f4b2bfed..572e2610e0a3 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -179,8 +179,7 @@ num-lanes = <4>; num-viewport = <8>; reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; - ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000 - 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", |