diff options
| author | Pierre Gondois <pierre.gondois@arm.com> | 2022-10-31 10:20:16 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2022-11-28 01:23:11 +0100 |
| commit | b5d971cf170e09fffc25b58b0de3cfdb0a1c342d (patch) | |
| tree | e64958925d2d6c9fb7f1ca6405a8c7b56ce50d8d /arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | |
| parent | 21aad8ba615e9c39cee6c5d0b76726f63791926c (diff) | |
arm64: dts: Update cache properties for marvell
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The recently added init_of_cache_level() function checks
these properties. Add them if missing.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index 3db427122f9e..a7b8e001cc9c 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -81,6 +81,7 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { @@ -88,6 +89,7 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; }; |