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authorMiquel Raynal <miquel.raynal@bootlin.com>2018-10-01 16:13:56 +0200
committerGregory CLEMENT <gregory.clement@bootlin.com>2018-10-02 16:46:53 +0200
commitb9a5950fc52763401fc774dfb0fccc02f0c9baf5 (patch)
treeeb0ea45024c3e2628bf5f279dffd2708a8062beb /arch/arm64/boot/dts/marvell/armada-ap806.dtsi
parent8ed46368776b3bc93d74c1f8f2bfb9fd8a9ad805 (diff)
arm64: dts: marvell: add AP806 SEI subnode
Add the System Error Interrupt node, representing an IRQ chip which is part of the GIC. The SEI node aggregates interrupts from the AP through wired interrupts, and from the CPs through MSIs. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-ap806.dtsi')
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806.dtsi9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 3032f04dde78..073610ac0a53 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -152,6 +152,15 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
+ sei: interrupt-controller@3f0200 {
+ compatible = "marvell,ap806-sei";
+ reg = <0x3f0200 0x40>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ msi-controller;
+ };
+
xor@400000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,