diff options
| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2019-10-04 16:27:27 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-09 09:36:41 +0200 |
| commit | 30d53abdc60a6515f02f181e7c39b7b23d5fb3aa (patch) | |
| tree | e341ec3afb790df3d052a87b7a3a17b2e5400b44 /arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | |
| parent | 760cabcd6ad23956542f953e5a617a8e0a81a792 (diff) | |
arm64: dts: marvell: Add AP807-quad cache description
Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi index 65364691257d..840466e143b4 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -22,6 +22,13 @@ enable-method = "psci"; #cooling-cells = <2>; clocks = <&cpu_clk 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_0>; }; cpu1: cpu@1 { device_type = "cpu"; @@ -30,6 +37,13 @@ enable-method = "psci"; #cooling-cells = <2>; clocks = <&cpu_clk 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_0>; }; cpu2: cpu@100 { device_type = "cpu"; @@ -38,6 +52,13 @@ enable-method = "psci"; #cooling-cells = <2>; clocks = <&cpu_clk 1>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; }; cpu3: cpu@101 { device_type = "cpu"; @@ -46,6 +67,27 @@ enable-method = "psci"; #cooling-cells = <2>; clocks = <&cpu_clk 1>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; }; |