diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-03-14 17:19:27 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-03-19 17:13:50 +0100 |
| commit | ef04faf106c430c3f830f93f3b2fb652b5537d7a (patch) | |
| tree | 027e57130442a5008184d92eed65d831956c23a2 /arch/arm64/boot/dts/marvell/armada-cp110.dtsi | |
| parent | 3c7f7f1503d20b14e22f64c27dc13522f5d60707 (diff) | |
ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node
This extra clock is needed to access the registers of the NAND controller
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "mtd: nand: marvell: Fix clock resource by adding
a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-cp110.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index b6947fcb8ce6..9ffb86b9441e 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -365,7 +365,9 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CP110_LABEL(clk) 1 2>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 2>, + <&CP110_LABEL(clk) 1 17>; marvell,system-controller = <&CP110_LABEL(syscon0)>; status = "disabled"; }; |