diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-03-14 17:19:24 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-03-19 17:13:41 +0100 |
| commit | f1ebfab99df1032166c531cd48f8f942d10fe190 (patch) | |
| tree | 46d87977cdc43dba9deb224e75a0ddd9feff6df0 /arch/arm64/boot/dts/marvell/armada-cp110.dtsi | |
| parent | f03ad7f6c5ca38242d9d23e6d1c087c43b66e481 (diff) | |
ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes
This extra clock is needed to access the registers of the XOR engine
controller used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by
adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-cp110.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index c35368d2a4cd..a51c553b5120 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -244,7 +244,9 @@ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; dma-coherent; msi-parent = <&gic_v2m0>; - clocks = <&CP110_LABEL(clk) 1 8>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 8>, + <&CP110_LABEL(clk) 1 14>; }; CP110_LABEL(xor1): xor@6c0000 { @@ -252,7 +254,9 @@ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; dma-coherent; msi-parent = <&gic_v2m0>; - clocks = <&CP110_LABEL(clk) 1 7>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 7>, + <&CP110_LABEL(clk) 1 14>; }; CP110_LABEL(spi0): spi@700600 { |