diff options
| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-10-04 16:27:31 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-09 09:36:41 +0200 |
| commit | 5f07b26e85dc86f017833ea745ff4e5b420280cd (patch) | |
| tree | 90365ccf131901d8243fb51545bcee29d6811a7e /arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | |
| parent | 1399672e48b573f6526b9ac78cfd50314f0b01a6 (diff) | |
arm64: dts: marvell: Externalize PCIe macros from CP11x file
PCIe macros are specific to CP110 and will not fit CP115
constraints. To keep the same way the files are organized, just move
some macros out of the CP11x generic file and define them directly in
SoC DTSI, instead of defining single addresses in the SoC DTSI and
reusing them in macros.
In the end:
* CP11X_PCIE_MEM_BASE SoC define is dropped
* CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the
SoC files as it replaces the above definition.
* As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with
newer SoCs, we put it in the SoC files as well.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-cp11x.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 7d1ab097453d..9dcf16beabf5 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -10,8 +10,7 @@ #include "armada-common.dtsi" -#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000)) -#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000) +#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) / { /* @@ -507,7 +506,7 @@ bus-range = <0 0xff>; /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; @@ -531,7 +530,7 @@ bus-range = <0 0xff>; /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; @@ -556,7 +555,7 @@ bus-range = <0 0xff>; /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>; + ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; |