diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2017-07-01 15:16:36 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-08-02 16:07:38 +0200 |
| commit | 395e66ba07aaec5ce37b61da158816d96d4b3ce1 (patch) | |
| tree | e2aec54274ae60593748cd582adbaf91e1c4c930 /arch/arm64/boot/dts/marvell | |
| parent | 5f926e889fcdb4aab32caf7ebe1c42dd7c2a4e64 (diff) | |
ARM64: dts: marvell: armada-37xx: Wire PMUv3
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a PMUv3, just like most ARMv8 cores.
Advertise the PMUv3 presence in the device tree, and wire its
interrupt. This allows the perf subsystem to work correctly.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index b6f1e7a5e5ec..8c0cf7efac65 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -81,6 +81,11 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; |