diff options
| author | Chen-Yu Tsai <wenst@chromium.org> | 2022-12-29 18:12:02 +0800 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2023-01-19 18:48:59 +0100 |
| commit | 089cd717e6ef03cf9cf7865777d67775de41339b (patch) | |
| tree | 56ba95fe4d28b437d738d7e2d5835feb7e86739c /arch/arm64/boot/dts/mediatek/mt8192.dtsi | |
| parent | 2d812e9e1dfd00e70c990a87c29c37db90977a5f (diff) | |
arm64: dts: mediatek: mt8192: Mark scp_adsp clock as broken
The scp_adsp clock controller is under the SCP_ADSP power domain. This
power domain is currently not supported nor defined.
Mark the clock controller as broken for now, to avoid the system from
trying to access it, and causing the CPU or bus to stall.
Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20221229101202.1655924-1-wenst@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8192.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index dd618c563e8a..ef4fcefa2bfc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -644,6 +644,8 @@ compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; #clock-cells = <1>; + /* power domain dependency not upstreamed */ + status = "fail"; }; uart0: serial@11002000 { |