diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-20 15:49:56 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-20 15:49:56 -0800 |
| commit | 950b6662e26e381cf8834b9b78b08261890ee697 (patch) | |
| tree | f6055bfca2a0c9e02724921e64cbde72905118e7 /arch/arm64/boot/dts/mediatek | |
| parent | c72e04c26faefc6650709066a8f019a7fb4cbb84 (diff) | |
| parent | e43efb6d713bca3855909a2f9caec280a2b0a503 (diff) | |
Merge tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC DT updates from Arnd Bergmann:
"About a quarter of the changes are for 32-bit arm, mostly filling in
device support for existing machines and adding minor cleanups, mostly
for Qualcomm and Samsung based machines.
Two new 32-bit SoCs are added, both are quad-core Cortex-A7 chips from
Rockchips that have been around for a while but were lacking kernel
support so far: RV1126 is a Vision SoC with an NPU and is used in the
Edgeble Neural Compute Module 2(Neu2) board, while RK3128 is design
for TV boxes and so far only comes with a dts for its refernece
design.
The other 32-bit boards that were added are two ASpeed AST2600 based
BMC boards, the Microchip sam9x60_curiosity development board (Armv5
based!), the Enclustra PE1 FPGA-SoM baseboard, and a few more boards
for i.MX53 and i.MX6ULL.
On the RISC-V side, there are fewer patches, but a total of ten new
single-board computers based on variations of the Allwinner D1/T113
chip, plus one more board based on Microchip Polarfire.
As usual, arm64 has by far the most changes here, with over 700
non-merge changesets, among them over 400 alone for Qualcomm. The
newly added SoCs this time are all recent high-end embedded SoCs for
various markets, each on comes with support for its reference board:
- Qualcomm SM8550 (Snapdragon 8 Gen 2) for mobile phones
- Qualcomm QDU1000/QRU1000 5G RAN platform
- Rockchips RK3588/RK3588s for tablets, chromebooks and SBCs
- TI J784S4 for industrial and automotive applications
In total, there are 46 new arm64 machines:
- Reference platforms for each of the five new SoCs
- Three Amlogic based development boards
- Six embedded machines based on NXP i.MX8MM and i.MX8MP
- The Mediatek mt7986a based Banana Pi R3 router
- Six tablets based on Qualcomm MSM8916 (Snapdragon 410), SM6115
(Snapdragon 662) and SM8250 (Snapdragon 865)
- Two LTE dongles, also based on MSM8916
- Seven mobile phones, based on Qualcomm MSM8953 (Snapdragon 610),
SDM450 and SDM632
- Three chromebooks based on Qualcomm SC7280 (Snapdragon 7c)
- Nine development boards based on Rockchips RK3588, RK3568, RK3566
and RK3328.
- Five development machines based on TI K3 (AM642/AM654/AM68/AM69)
The cleanup of dtc warnings continues across all platforms, adding to
the total number of changes"
* tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (1035 commits)
dt-bindings: riscv: correct starfive visionfive 2 compatibles
ARM: dts: socfpga: Add enclustra PE1 devicetree
dt-bindings: altera: Add enclustra mercury PE1
arm64: dts: qcom: msm8996: align RPM G-Link clock-controller node with bindings
arm64: dts: qcom: qcs404: align RPM G-Link node with bindings
arm64: dts: qcom: ipq6018: align RPM G-Link node with bindings
arm64: dts: qcom: sm8550: remove invalid interconnect property from cryptobam
arm64: dts: qcom: sc7280: Adjust zombie PWM frequency
arm64: dts: qcom: sc8280xp-pmics: Specify interrupt parent explicitly
arm64: dts: qcom: sm7225-fairphone-fp4: enable remaining i2c busses
arm64: dts: qcom: sm7225-fairphone-fp4: move status property down
arm64: dts: qcom: pmk8350: Use the correct PON compatible
arm64: dts: qcom: sc8280xp-x13s: Enable external display
arm64: dts: qcom: sc8280xp-crd: Introduce pmic_glink
arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks
arm64: dts: qcom: sm8350-hdk: enable GPU
arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
arm64: dts: qcom: sm8350: finish reordering nodes
arm64: dts: qcom: sm8350: move more nodes to correct place
arm64: dts: qcom: sm8350: reorder device nodes
...
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
39 files changed, 2760 insertions, 110 deletions
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 813e735c5b96..d5cd7b3e09cf 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -8,6 +8,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 92212cddd37e..879dff24dcd3 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -270,7 +270,6 @@ compatible = "mediatek,mt2712-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi index 98f3b0e0c9f6..b605313bed99 100644 --- a/arch/arm64/boot/dts/mediatek/mt6358.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi @@ -5,7 +5,7 @@ #include <dt-bindings/input/input.h> &pwrap { - pmic: mt6358 { + pmic: pmic { compatible = "mediatek,mt6358"; interrupt-controller; interrupt-parent = <&pio>; @@ -355,11 +355,11 @@ }; }; - mt6358rtc: mt6358rtc { + mt6358rtc: rtc { compatible = "mediatek,mt6358-rtc"; }; - mt6358keys: mt6358keys { + mt6358keys: keys { compatible = "mediatek,mt6358-keys"; power { linux,keycodes = <KEY_POWER>; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index bb575837e4ce..b3fc76d837a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -40,6 +40,12 @@ enable-method = "psci"; reg = <0x001>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; }; @@ -49,6 +55,12 @@ enable-method = "psci"; reg = <0x002>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; }; @@ -58,6 +70,12 @@ enable-method = "psci"; reg = <0x003>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; }; @@ -67,6 +85,12 @@ enable-method = "psci"; reg = <0x100>; cci-control-port = <&cci_control1>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_1>; }; @@ -76,6 +100,12 @@ enable-method = "psci"; reg = <0x101>; cci-control-port = <&cci_control1>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_1>; }; @@ -85,6 +115,12 @@ enable-method = "psci"; reg = <0x102>; cci-control-port = <&cci_control1>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_1>; }; @@ -94,6 +130,12 @@ enable-method = "psci"; reg = <0x103>; cci-control-port = <&cci_control1>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_1>; }; @@ -138,11 +180,19 @@ l2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; }; l2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 146e18b5b1f4..20129bc98e21 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -435,6 +435,7 @@ pwm: pwm@11006000 { compatible = "mediatek,mt7622-pwm"; reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM_PD>, @@ -526,7 +527,6 @@ reg = <0 0x1100c000 0 0x1000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; clocks = <&pericfg CLK_PERI_BTIF_PD>; - clock-names = "main"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso new file mode 100644 index 000000000000..779dc6782bb1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso new file mode 100644 index 000000000000..15ee8c568f3c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Authors: Daniel Golle <daniel@makrotopia.org> + * Frank Wunderlich <frank-w@public-files.de> + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "reserved"; + reg = <0x80000 0x300000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso new file mode 100644 index 000000000000..84aa229e80f3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Authors: Daniel Golle <daniel@makrotopia.org> + * Frank Wunderlich <frank-w@public-files.de> + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "reserved"; + reg = <0x20000 0x20000>; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved2"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso new file mode 100644 index 000000000000..f623bce075ce --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + status = "okay"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts new file mode 100644 index 000000000000..33bd6febc160 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Authors: Sam.Shih <sam.shih@mediatek.com> + * Frank Wunderlich <frank-w@public-files.de> + * Daniel Golle <daniel@makrotopia.org> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPI-R3"; + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcin: regulator-12vd { + compatible = "regulator-fixed"; + regulator-name = "12vd"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset-key { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps-key { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + /* i2c of the left SFP cage (wan) */ + i2c_sfp1: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* i2c of the right SFP cage (lan) */ + i2c_sfp2: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_POWER; + gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + blue_led: led-1 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&pio 86 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1.8vd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3.3vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + /* left SFP cage (wan) */ + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + /* right SFP cage (lan) */ + sfp2: sfp-2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@31 { + compatible = "mediatek,mt7531"; + reg = <31>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_pereset"; + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_0"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_rx_tx"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_0_rx_tx"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_led_pins: wf-led-pins { + mux { + function = "led"; + groups = "wifi_led"; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + status = "okay"; +}; + +&ssusb { + status = "okay"; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan0"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + port5: port@5 { + reg = <5>; + label = "lan4"; + phy-mode = "2500base-x"; + sfp = <&sfp2>; + managed = "in-band-status"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 9b83925893b7..4f18b4a9a8c8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -5,6 +5,8 @@ */ /dts-v1/; +#include <dt-bindings/pinctrl/mt65xx.h> + #include "mt7986a.dtsi" / { @@ -23,6 +25,24 @@ device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &crypto { @@ -58,7 +78,99 @@ }; }; +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + &pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + spi_flash_pins: spi-flash-pins { mux { function = "spi"; @@ -140,6 +252,10 @@ status = "okay"; }; +&ssusb { + status = "okay"; +}; + &switch { ports { #address-cells = <1>; @@ -201,6 +317,10 @@ status = "okay"; }; +&usb_phy { + status = "okay"; +}; + &wifi { status = "okay"; pinctrl-names = "default", "dbdc"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 0e9406fc63e2..51944690e790 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt7986-clk.h> #include <dt-bindings/reset/mt7986-resets.h> +#include <dt-bindings/phy/phy.h> / { compatible = "mediatek,mt7986a"; @@ -167,8 +168,7 @@ }; watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt7986-wdt"; reg = <0 0x1001c000 0 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; @@ -323,6 +323,127 @@ status = "disabled"; }; + ssusb: usb@11200000 { + compatible = "mediatek,mt7986-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", + "ref_ck", + "mcu_ck", + "dma_ck", + "xhci_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11c20000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, + <&infracfg CLK_INFRA_MSDC_HCK_CK>, + <&infracfg CLK_INFRA_MSDC_CK>, + <&infracfg CLK_INFRA_MSDC_133M_CK>, + <&infracfg CLK_INFRA_MSDC_66M_CK>; + clock-names = "source", "hclk", "source_cg", "bus_clk", + "sys_cg"; + status = "disabled"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x00 0x11280000 0x00 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x10000000>; + clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + status = "disabled"; + + phys = <&pcie_port PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie_phy: t-phy@11c00000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + pcie_port: pcie-phy@11c00000 { + reg = <0 0x11c00000 0 0x20000>; + clocks = <&clk40m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e10000 0x1700>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, + <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@1000 { + reg = <0x1000 0x700>; + clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, + <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + ethsys: syscon@15000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 243760cd3011..188ce82ae56c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -167,10 +167,18 @@ status = "okay"; }; +&ssusb { + status = "okay"; +}; + &uart0 { status = "okay"; }; +&usb_phy { + status = "okay"; +}; + &wifi { status = "okay"; pinctrl-names = "default", "dbdc"; diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index fbe1a1128cc6..6a54315cf650 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -117,7 +117,6 @@ compatible = "mediatek,mt8167-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl>; - pins-are-numbered; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index e21feb85d822..d452cab28c67 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -90,18 +90,6 @@ }; }; - panel: panel { - compatible = "lg,lp120up1"; - power-supply = <&panel_fixed_3v3>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&ps8640_out>; - }; - }; - }; - panel_fixed_3v3: regulator1 { compatible = "regulator-fixed"; regulator-name = "PANEL_3V3"; @@ -161,6 +149,18 @@ }; }; }; + + watchdog { + compatible = "arm,smc-wdt"; + }; +}; + +/* + * Disable the original MMIO watch dog and switch to the SMC watchdog, which + * operates on the same MMIO. + */ +&watchdog { + status = "disabled"; }; &mfg_async { @@ -282,6 +282,20 @@ }; }; }; + + aux-bus { + panel: panel { + compatible = "lg,lp120up1"; + power-supply = <&panel_fixed_3v3>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; + }; + }; }; }; @@ -913,7 +927,7 @@ }; &pwrap { - pmic: mt6397 { + pmic: pmic { compatible = "mediatek,mt6397"; #address-cells = <1>; #size-cells = <1>; @@ -929,7 +943,6 @@ pio6397: pinctrl { compatible = "mediatek,mt6397-pinctrl"; - pins-are-numbered; gpio-controller; #gpio-cells = <2>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 0b5f154007be..755df5694234 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -300,7 +300,7 @@ /* Only MT8173 E1 needs USB power domain */ power-domains = <&spm MT8173_POWER_DOMAIN_USB>; - pmic: mt6397 { + pmic: pmic { compatible = "mediatek,mt6397"; interrupt-parent = <&pio>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 7640b5158ff9..c47d7d900f28 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -375,7 +375,6 @@ compatible = "mediatek,mt8173-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index dec11a4eb59e..77b96ddf648e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -13,7 +13,7 @@ pwmleds { compatible = "pwm-leds"; - keyboard_backlight: keyboard-backlight { + keyboard_backlight: led-0 { label = "cros_ec::kbd_backlight"; pwms = <&cros_ec_pwm 0>; max-brightness = <1023>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 3ac83be53627..bf97b60ae4d1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -4,20 +4,10 @@ */ #include "mt8183-kukui.dtsi" +/* Must come after mt8183-kukui.dtsi to modify cros_ec */ +#include <arm/cros-ec-keyboard.dtsi> / { - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&pp3300_panel>; - backlight = <&backlight_lcd0>; - - port { - panel_in: endpoint { - remote-endpoint = <&anx7625_out>; - }; - }; - }; - pp1200_mipibrdg: pp1200-mipibrdg { compatible = "regulator-fixed"; regulator-name = "pp1200_mipibrdg"; @@ -181,6 +171,20 @@ remote-endpoint = <&panel_in>; }; }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <&pp3300_panel>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&anx7625_out>; + }; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi index 50a0dd36b5fb..a11adeb29b1f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -372,6 +372,12 @@ }; }; +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + &qca_wifi { qcom,ath10k-calibration-variant = "GO_KAKADU"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index 06f8c80bf553..4864c39e53a4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -339,6 +339,12 @@ }; }; +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + &qca_wifi { qcom,ath10k-calibration-variant = "GO_KODAMA"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi index a7b0cb3ff7b0..d5f41c6c9881 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -343,6 +343,12 @@ }; }; +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + &qca_wifi { qcom,ath10k-calibration-variant = "LE_Krane"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 7fc4c592a908..fbe14b13051a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -963,6 +963,7 @@ pinctrl-0 = <&uart1_pins_default>; pinctrl-1 = <&uart1_pins_sleep>; status = "okay"; + /delete-property/ interrupts; interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, <&pio 121 IRQ_TYPE_EDGE_FALLING>; @@ -989,5 +990,4 @@ }; }; -#include <arm/cros-ec-keyboard.dtsi> #include <arm/cros-ec-sbs.dtsi> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 402136bfd535..3d1d7870a5f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -336,6 +336,13 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; #cooling-cells = <2>; mediatek,cci = <&cci>; }; @@ -352,6 +359,13 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; #cooling-cells = <2>; mediatek,cci = <&cci>; }; @@ -368,6 +382,13 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; #cooling-cells = <2>; mediatek,cci = <&cci>; }; @@ -384,6 +405,13 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; #cooling-cells = <2>; mediatek,cci = <&cci>; }; @@ -400,6 +428,13 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; #cooling-cells = <2>; mediatek,cci = <&cci>; }; @@ -416,6 +451,13 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; #cooling-cells = <2>; mediatek,cci = <&cci>; }; @@ -432,6 +474,13 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; #cooling-cells = <2>; mediatek,cci = <&cci>; }; @@ -448,6 +497,13 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; #cooling-cells = <2>; mediatek,cci = <&cci>; }; @@ -481,6 +537,24 @@ min-residency-us = <1300>; }; }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; + }; }; gpu_opp_table: opp-table-0 { @@ -585,6 +659,15 @@ method = "smc"; }; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; @@ -968,8 +1051,7 @@ "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen CLK_TOP_CLK13M>; - clock-names = "clk13m"; + clocks = <&clk13m>; }; iommu: iommu@10205000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index c326aeb33a10..a0d3e1f731bd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/mt8186-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/memory/mt8186-memory-port.h> #include <dt-bindings/pinctrl/mt8186-pinfunc.h> #include <dt-bindings/power/mt8186-power.h> #include <dt-bindings/phy/phy.h> @@ -47,14 +48,12 @@ core5 { cpu = <&cpu5>; }; - }; - cluster1 { - core0 { + core6 { cpu = <&cpu6>; }; - core1 { + core7 { cpu = <&cpu7>; }; }; @@ -67,7 +66,13 @@ enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -79,7 +84,13 @@ enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -91,7 +102,13 @@ enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -103,7 +120,13 @@ enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -115,7 +138,13 @@ enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -127,7 +156,13 @@ enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <382>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -139,7 +174,13 @@ enable-method = "psci"; clock-frequency = <2050000000>; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&cpu_off_b &cluster_off_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -151,7 +192,13 @@ enable-method = "psci"; clock-frequency = <2050000000>; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&cpu_off_b &cluster_off_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -159,7 +206,7 @@ idle-states { entry-method = "psci"; - cpu_off_l: cpu-off-l { + cpu_ret_l: cpu-retention-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; @@ -168,7 +215,7 @@ min-residency-us = <1600>; }; - cpu_off_b: cpu-off-b { + cpu_ret_b: cpu-retention-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; @@ -177,7 +224,7 @@ min-residency-us = <1400>; }; - cluster_off_l: cluster-off-l { + cpu_off_l: cpu-off-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; @@ -186,7 +233,7 @@ min-residency-us = <2100>; }; - cluster_off_b: cluster-off-b { + cpu_off_b: cpu-off-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; @@ -199,25 +246,37 @@ l2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; }; }; - clk13m: oscillator-13m { - compatible = "fixed-clock"; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; #clock-cells = <0>; - clock-frequency = <13000000>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; clock-output-names = "clk13m"; }; @@ -332,9 +391,196 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8186-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { + reg = <MT8186_POWER_DOMAIN_MFG0>; + clocks = <&topckgen CLK_TOP_MFG>; + clock-names = "mfg00"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_MFG1 { + reg = <MT8186_POWER_DOMAIN_MFG1>; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_MFG2 { + reg = <MT8186_POWER_DOMAIN_MFG2>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_MFG3 { + reg = <MT8186_POWER_DOMAIN_MFG3>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { + reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; + clocks = <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>; + clock-names = "csirx_top0", "csirx_top1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_SSUSB { + reg = <MT8186_POWER_DOMAIN_SSUSB>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { + reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_ADSP_AO { + reg = <MT8186_POWER_DOMAIN_ADSP_AO>; + clocks = <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + clock-names = "audioadsp", "adsp_bus"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { + reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { + reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_CONN_ON { + reg = <MT8186_POWER_DOMAIN_CONN_ON>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_DIS { + reg = <MT8186_POWER_DOMAIN_DIS>; + clocks = <&topckgen CLK_TOP_DISP>, + <&topckgen CLK_TOP_MDP>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "disp", "mdp", "smi_infra", "smi_common", + "smi_gals", "smi_iommu"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_VDEC { + reg = <MT8186_POWER_DOMAIN_VDEC>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "vdec0", "larb"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_CAM { + reg = <MT8186_POWER_DOMAIN_CAM>; + clocks = <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>, + <&topckgen CLK_TOP_SENINF2>, + <&topckgen CLK_TOP_SENINF3>, + <&topckgen CLK_TOP_CAMTM>, + <&camsys CLK_CAM2MM_GALS>; + clock-names = "cam-top", "cam0", "cam1", "cam2", + "cam3", "cam-tm", "gals"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { + reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { + reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_IMG { + reg = <MT8186_POWER_DOMAIN_IMG>; + clocks = <&topckgen CLK_TOP_IMG1>, + <&imgsys1 CLK_IMG1_GALS_IMG1>; + clock-names = "img-top", "gals"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_IMG2 { + reg = <MT8186_POWER_DOMAIN_IMG2>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_IPE { + reg = <MT8186_POWER_DOMAIN_IPE>; + clocks = <&topckgen CLK_TOP_IPE>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS_IPE>; + clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", + "ipe-smi", "ipe-gals"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_VENC { + reg = <MT8186_POWER_DOMAIN_VENC>; + clocks = <&topckgen CLK_TOP_VENC>, + <&vencsys CLK_VENC_CKE1_VENC>; + clock-names = "venc0", "larb"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_WPE { + reg = <MT8186_POWER_DOMAIN_WPE>; + clocks = <&topckgen CLK_TOP_WPE>, + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; + clock-names = "wpe0", "larb-ck", "larb-pclk"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + }; + watchdog: watchdog@10007000 { - compatible = "mediatek,mt8186-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8186-wdt"; mediatek,disable-extrst; reg = <0 0x10007000 0 0x1000>; #reset-cells = <1>; @@ -372,6 +618,20 @@ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; }; + adsp_mailbox0: mailbox@10686000 { + compatible = "mediatek,mt8186-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10686100 0 0x1000>; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + adsp_mailbox1: mailbox@10687000 { + compatible = "mediatek,mt8186-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10687100 0 0x1000>; + interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; + }; + nor_flash: spi@11000000 { compatible = "mediatek,mt8186-nor"; reg = <0 0x11000000 0 0x1000>; @@ -659,15 +919,78 @@ status = "disabled"; }; + afe: audio-controller@11210000 { + compatible = "mediatek,mt8186-sound"; + reg = <0 0x11210000 0 0x2000>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_AUDIO>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_MAINPLL_D2_D4>, + <&topckgen CLK_TOP_AUD_1>, + <&apmixedsys CLK_APMIXED_APLL1>, + <&topckgen CLK_TOP_AUD_2>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_AUD_ENGEN2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, + <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, + <&topckgen CLK_TOP_APLL12_CK_DIV0>, + <&topckgen CLK_TOP_APLL12_CK_DIV1>, + <&topckgen CLK_TOP_APLL12_CK_DIV2>, + <&topckgen CLK_TOP_APLL12_CK_DIV4>, + <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, + <&topckgen CLK_TOP_AUDIO_H>, + <&clk26m>; + clock-names = "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s4_m_sel", + "top_tdm_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div4", + "top_apll12_div_tdm", + "top_mux_audio_h", + "top_clk26m_clk"; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,apmixedsys = <&apmixedsys>; + mediatek,infracfg = <&infracfg_ao>; + mediatek,topckgen = <&topckgen>; + resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; - reg = <0 0x11230000 0 0x1000>, + reg = <0 0x11230000 0 0x10000>, <0 0x11cd0000 0 0x1000>; clocks = <&topckgen CLK_TOP_MSDC50_0>, <&infracfg_ao CLK_INFRA_AO_MSDC0>, - <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; - clock-names = "source", "hclk", "source_cg"; + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, + <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; + clock-names = "source", "hclk", "source_cg", "crypto"; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; @@ -759,24 +1082,149 @@ #reset-cells = <1>; }; + smi_common: smi@14002000 { + compatible = "mediatek,mt8186-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + larb0: smi@14003000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + larb1: smi@14004000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x14004000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + dpi: dpi@1400a000 { + compatible = "mediatek,mt8186-dpi"; + reg = <0 0x1400a000 0 0x1000>; + clocks = <&topckgen CLK_TOP_DPI>, + <&mmsys CLK_MM_DISP_DPI>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + assigned-clocks = <&topckgen CLK_TOP_DPI>; + assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; + status = "disabled"; + + port { + dpi_out: endpoint { }; + }; + }; + + dsi0: dsi@14013000 { + compatible = "mediatek,mt8186-dsi"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + + iommu_mm: iommu@14016000 { + compatible = "mediatek,mt8186-iommu-mm"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "bclk"; + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 + &larb7 &larb8 &larb9 &larb11 + &larb13 &larb14 &larb16 &larb17 + &larb19 &larb20>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + #iommu-cells = <1>; + }; + wpesys: clock-controller@14020000 { compatible = "mediatek,mt8186-wpesys"; reg = <0 0x14020000 0 0x1000>; #clock-cells = <1>; }; + larb8: smi@14023000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x14023000 0 0x1000>; + clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; + clock-names = "apb", "smi"; + mediatek,larb-id = <8>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; + }; + imgsys1: clock-controller@15020000 { compatible = "mediatek,mt8186-imgsys1"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; + larb9: smi@1502e000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1502e000 0 0x1000>; + clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, + <&imgsys1 CLK_IMG1_LARB9_IMG1>; + clock-names = "apb", "smi"; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; + }; + imgsys2: clock-controller@15820000 { compatible = "mediatek,mt8186-imgsys2"; reg = <0 0x15820000 0 0x1000>; #clock-cells = <1>; }; + larb11: smi@1582e000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1582e000 0 0x1000>; + clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, + <&imgsys2 CLK_IMG2_LARB9_IMG2>; + clock-names = "apb", "smi"; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; + }; + + larb4: smi@1602e000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1602e000 0 0x1000>; + clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "apb", "smi"; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; + }; + vdecsys: clock-controller@1602f000 { compatible = "mediatek,mt8186-vdecsys"; reg = <0 0x1602f000 0 0x1000>; @@ -789,12 +1237,65 @@ #clock-cells = <1>; }; + larb7: smi@17010000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + clocks = <&vencsys CLK_VENC_CKE1_VENC>, + <&vencsys CLK_VENC_CKE1_VENC>; + clock-names = "apb", "smi"; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8186-camsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + larb13: smi@1a001000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; + clock-names = "apb", "smi"; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; + }; + + larb14: smi@1a002000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; + }; + + larb16: smi@1a00f000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1a00f000 0 0x1000>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; + clock-names = "apb", "smi"; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: smi@1a010000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; + clock-names = "apb", "smi"; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible = "mediatek,mt8186-camsys_rawa"; reg = <0 0x1a04f000 0 0x1000>; @@ -813,10 +1314,40 @@ #clock-cells = <1>; }; + larb2: smi@1b002000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1b002000 0 0x1000>; + clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; + clock-names = "apb", "smi"; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + ipesys: clock-controller@1c000000 { compatible = "mediatek,mt8186-ipesys"; reg = <0 0x1c000000 0 0x1000>; #clock-cells = <1>; }; + + larb20: smi@1c00f000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1c00f000 0 0x1000>; + clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; + clock-names = "apb", "smi"; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; + }; + + larb19: smi@1c10f000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1c10f000 0 0x1000>; + clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; + clock-names = "apb", "smi"; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi new file mode 100644 index 000000000000..f521f50d448f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p-rt5682.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + */ + +#include "mt8192-asurada-audio-rt5682.dtsi" +#include "mt8192-asurada-audio-rt1015p.dtsi" + +&sound { + compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682"; + + speaker-codecs { + sound-dai = <&rt1015p>; + }; + + headset-codec { + sound-dai = <&rt5682 0>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi new file mode 100644 index 000000000000..e5743789934e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt1015p.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/mt8192-pinfunc.h> + +/ { + rt1015p: audio-codec { + compatible = "realtek,rt1015p"; + pinctrl-names = "default"; + pinctrl-0 = <&rt1015p_pins>; + sdb-gpios = <&pio 147 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&pio { + rt1015p_pins: rt1015p-default-pins { + pins { + pinmux = <PINMUX_GPIO147__FUNC_GPIO147>; + output-low; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi new file mode 100644 index 000000000000..05e48b870a92 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-audio-rt5682.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ + +&i2c1 { + rt5682: audio-codec@1a { + compatible = "realtek,rt5682i"; + reg = <0x1a>; + interrupts-extended = <&pio 18 IRQ_TYPE_LEVEL_LOW>; + realtek,jd-src = <1>; + realtek,btndet-delay = <16>; + #sound-dai-cells = <1>; + + AVDD-supply = <&mt6359_vio18_ldo_reg>; + DBVDD-supply = <&mt6359_vio18_ldo_reg>; + LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; + MICVDD-supply = <&pp3300_g>; + VBAT-supply = <&pp3300_ldo_z>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index 1e91491945f6..43a823990a92 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -4,6 +4,7 @@ */ /dts-v1/; #include "mt8192-asurada.dtsi" +#include "mt8192-asurada-audio-rt1015p-rt5682.dtsi" / { model = "Google Hayato rev1"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index fa3d9573f37a..c6ad10cec95e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -4,6 +4,7 @@ */ /dts-v1/; #include "mt8192-asurada.dtsi" +#include "mt8192-asurada-audio-rt1015p-rt5682.dtsi" #include <dt-bindings/leds/common.h> / { diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 4b314435f8fd..9f12257ab4e7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -11,6 +11,13 @@ / { aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c7 = &i2c7; + mmc0 = &mmc0; + mmc1 = &mmc1; serial0 = &uart0; }; @@ -23,6 +30,59 @@ reg = <0 0x40000000 0 0x80000000>; }; + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000>; + power-supply = <&ppvar_sys>; + enable-gpios = <&pio 152 0>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + }; + + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <50>; + }; + + pp1000_dpbrdg: regulator-1v0-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1000_dpbrdg_en_pins>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 19 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6359_vs2_buck_reg>; + }; + + pp1000_mipibrdg: regulator-1v0-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1000_mipibrdg_en_pins>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6359_vs2_buck_reg>; + }; + + pp1800_dpbrdg: regulator-1v8-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1800_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_dpbrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 126 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6359_vio18_ldo_reg>; + }; + /* system wide LDO 1.8V power rail */ pp1800_ldo_g: regulator-1v8-g { compatible = "regulator-fixed"; @@ -34,6 +94,28 @@ vin-supply = <&pp3300_g>; }; + pp1800_mipibrdg: regulator-1v8-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1800_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_mipibrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 128 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6359_vio18_ldo_reg>; + }; + + pp3300_dpbrdg: regulator-3v3-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp3300_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_dpbrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 26 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_g>; + }; + /* system wide switching 3.3V power rail */ pp3300_g: regulator-3v3-g { compatible = "regulator-fixed"; @@ -56,6 +138,17 @@ vin-supply = <&ppvar_sys>; }; + pp3300_mipibrdg: regulator-3v3-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp3300_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_mipibrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 127 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_g>; + }; + /* separately switched 3.3V power rail */ pp3300_u: regulator-3v3-u { compatible = "regulator-fixed"; @@ -116,6 +209,70 @@ reg = <0 0xc0000000 0 0x4000000>; }; }; + + sound: sound { + mediatek,platform = <&afe>; + pinctrl-names = "aud_clk_mosi_off", + "aud_clk_mosi_on", + "aud_dat_mosi_off", + "aud_dat_mosi_on", + "aud_dat_miso_off", + "aud_dat_miso_on", + "vow_dat_miso_off", + "vow_dat_miso_on", + "vow_clk_miso_off", + "vow_clk_miso_on", + "aud_nle_mosi_off", + "aud_nle_mosi_on", + "aud_dat_miso2_off", + "aud_dat_miso2_on", + "aud_gpio_i2s3_off", + "aud_gpio_i2s3_on", + "aud_gpio_i2s8_off", + "aud_gpio_i2s8_on", + "aud_gpio_i2s9_off", + "aud_gpio_i2s9_on", + "aud_dat_mosi_ch34_off", + "aud_dat_mosi_ch34_on", + "aud_dat_miso_ch34_off", + "aud_dat_miso_ch34_on", + "aud_gpio_tdm_off", + "aud_gpio_tdm_on"; + pinctrl-0 = <&aud_clk_mosi_off_pins>; + pinctrl-1 = <&aud_clk_mosi_on_pins>; + pinctrl-2 = <&aud_dat_mosi_off_pins>; + pinctrl-3 = <&aud_dat_mosi_on_pins>; + pinctrl-4 = <&aud_dat_miso_off_pins>; + pinctrl-5 = <&aud_dat_miso_on_pins>; + pinctrl-6 = <&vow_dat_miso_off_pins>; + pinctrl-7 = <&vow_dat_miso_on_pins>; + pinctrl-8 = <&vow_clk_miso_off_pins>; + pinctrl-9 = <&vow_clk_miso_on_pins>; + pinctrl-10 = <&aud_nle_mosi_off_pins>; + pinctrl-11 = <&aud_nle_mosi_on_pins>; + pinctrl-12 = <&aud_dat_miso2_off_pins>; + pinctrl-13 = <&aud_dat_miso2_on_pins>; + pinctrl-14 = <&aud_gpio_i2s3_off_pins>; + pinctrl-15 = <&aud_gpio_i2s3_on_pins>; + pinctrl-16 = <&aud_gpio_i2s8_off_pins>; + pinctrl-17 = <&aud_gpio_i2s8_on_pins>; + pinctrl-18 = <&aud_gpio_i2s9_off_pins>; + pinctrl-19 = <&aud_gpio_i2s9_on_pins>; + pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; + pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; + pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; + pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; + pinctrl-24 = <&aud_gpio_tdm_off_pins>; + pinctrl-25 = <&aud_gpio_tdm_on_pins>; + }; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi_out { + remote-endpoint = <&anx7625_in>; }; &i2c0 { @@ -166,6 +323,53 @@ clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; + + anx_bridge: anx7625@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&anx7625_pins>; + enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1000_mipibrdg>; + vdd18-supply = <&pp1800_mipibrdg>; + vdd33-supply = <&pp3300_mipibrdg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <&pp3300_mipibrdg>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&anx7625_out>; + }; + }; + }; + }; + }; }; &i2c7 { @@ -176,6 +380,10 @@ pinctrl-0 = <&i2c7_pins>; }; +&mipi_tx0 { + status = "okay"; +}; + &mmc0 { status = "okay"; @@ -507,6 +715,179 @@ "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + anx7625_pins: anx7625-default-pins { + pins-out { + pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, + <PINMUX_GPIO42__FUNC_GPIO42>; + output-low; + }; + + pins-in { + pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; + input-enable; + bias-pull-up; + }; + }; + + aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { + pins-mosi-off { + pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, + <PINMUX_GPIO215__FUNC_GPIO215>; + }; + }; + + aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { + pins-mosi-on { + pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, + <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; + drive-strength = <10>; + }; + }; + + aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { + pins-miso-off { + pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; + }; + }; + + aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { + pins-miso-on { + pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; + }; + }; + + aud_dat_miso_off_pins: aud-dat-miso-off-pins { + pins-miso-off { + pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, + <PINMUX_GPIO219__FUNC_GPIO219>; + }; + }; + + aud_dat_miso_on_pins: aud-dat-miso-on-pins { + pins-miso-on { + pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, + <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; + drive-strength = <10>; + }; + }; + + aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { + pins-miso-off { + pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; + }; + }; + + aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { + pins-miso-on { + pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; + }; + }; + + aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { + pins-mosi-off { + pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; + }; + }; + + aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { + pins-mosi-on { + pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; + }; + }; + + aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { + pins-mosi-off { + pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, + <PINMUX_GPIO217__FUNC_GPIO217>; + }; + }; + + aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { + pins-mosi-on { + pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, + <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; + drive-strength = <10>; + }; + }; + + aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { + pins-i2s3-off { + pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, + <PINMUX_GPIO33__FUNC_GPIO33>, + <PINMUX_GPIO35__FUNC_GPIO35>; + }; + }; + + aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { + pins-i2s3-on { + pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, + <PINMUX_GPIO33__FUNC_I2S3_LRCK>, + <PINMUX_GPIO35__FUNC_I2S3_DO>; + }; + }; + + aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { + pins-i2s8-off { + pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, + <PINMUX_GPIO11__FUNC_GPIO11>, + <PINMUX_GPIO12__FUNC_GPIO12>, + <PINMUX_GPIO13__FUNC_GPIO13>; + }; + }; + + aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { + pins-i2s8-on { + pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, + <PINMUX_GPIO11__FUNC_I2S8_BCK>, + <PINMUX_GPIO12__FUNC_I2S8_LRCK>, + <PINMUX_GPIO13__FUNC_I2S8_DI>; + }; + }; + + aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { + pins-i2s9-off { + pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; + }; + }; + + aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { + pins-i2s9-on { + pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; + }; + }; + + aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { + pins-tdm-off { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, + <PINMUX_GPIO1__FUNC_GPIO1>, + <PINMUX_GPIO2__FUNC_GPIO2>, + <PINMUX_GPIO3__FUNC_GPIO3>; + }; + }; + + aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { + pins-tdm-on { + pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, + <PINMUX_GPIO1__FUNC_TDM_BCK>, + <PINMUX_GPIO2__FUNC_TDM_MCK>, + <PINMUX_GPIO3__FUNC_TDM_DATA0>; + }; + }; + + aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { + pins-nle-mosi-off { + pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, + <PINMUX_GPIO198__FUNC_GPIO198>; + }; + }; + + aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { + pins-nle-mosi-on { + pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, + <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; + }; + }; + cr50_int: cr50-irq-default-pins { pins-gsc-ap-int-odl { pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; @@ -719,6 +1100,48 @@ }; }; + pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { + pins-en { + pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; + output-low; + }; + }; + + pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { + pins-en { + pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; + output-low; + }; + }; + + pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { + pins-en { + pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; + output-low; + }; + }; + + pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { + pins-en { + pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; + output-low; + }; + }; + + pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { + pins-en { + pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; + output-low; + }; + }; + + pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { + pins-en { + pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; + output-low; + }; + }; + pp3300_wlan_pins: pp3300-wlan-pins { pins-pcie-en-pp3300-wlan { pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; @@ -726,6 +1149,17 @@ }; }; + pwm0_pins: pwm0-default-pins { + pins-pwm { + pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; + }; + + pins-inhibit { + pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; + output-high; + }; + }; + scp_pins: scp-pins { pins-vreq-vao { pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; @@ -781,12 +1215,43 @@ output-low; }; }; + + vow_clk_miso_off_pins: vow-clk-miso-off-pins { + pins-miso-off { + pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; + }; + }; + + vow_clk_miso_on_pins: vow-clk-miso-on-pins { + pins-miso-on { + pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; + }; + }; + + vow_dat_miso_off_pins: vow-dat-miso-off-pins { + pins-miso-off { + pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; + }; + }; + + vow_dat_miso_on_pins: vow-dat-miso-on-pins { + pins-miso-on { + pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; + }; + }; }; &pmic { interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; }; +&pwm0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; +}; + &scp { status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 424fc89cc6f7..87b91c8feaf9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -29,6 +29,15 @@ rdma4 = &rdma4; }; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -53,7 +62,13 @@ reg = <0x000>; enable-method = "psci"; clock-frequency = <1701000000>; - cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; }; @@ -64,7 +79,13 @@ reg = <0x100>; enable-method = "psci"; clock-frequency = <1701000000>; - cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; }; @@ -75,7 +96,13 @@ reg = <0x200>; enable-method = "psci"; clock-frequency = <1701000000>; - cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; }; @@ -86,7 +113,13 @@ reg = <0x300>; enable-method = "psci"; clock-frequency = <1701000000>; - cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; }; @@ -97,7 +130,13 @@ reg = <0x400>; enable-method = "psci"; clock-frequency = <2171000000>; - cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; }; @@ -108,7 +147,13 @@ reg = <0x500>; enable-method = "psci"; clock-frequency = <2171000000>; - cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; }; @@ -119,7 +164,13 @@ reg = <0x600>; enable-method = "psci"; clock-frequency = <2171000000>; - cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; }; @@ -130,7 +181,13 @@ reg = <0x700>; enable-method = "psci"; clock-frequency = <2171000000>; - cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; }; @@ -149,19 +206,16 @@ core3 { cpu = <&cpu3>; }; - }; - - cluster1 { - core0 { + core4 { cpu = <&cpu4>; }; - core1 { + core5 { cpu = <&cpu5>; }; - core2 { + core6 { cpu = <&cpu6>; }; - core3 { + core7 { cpu = <&cpu7>; }; }; @@ -170,23 +224,33 @@ l2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; }; idle-states { entry-method = "psci"; - cpu_sleep_l: cpu-sleep-l { + cpu_ret_l: cpu-retention-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; @@ -194,7 +258,7 @@ exit-latency-us = <140>; min-residency-us = <780>; }; - cpu_sleep_b: cpu-sleep-b { + cpu_ret_b: cpu-retention-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; @@ -202,7 +266,7 @@ exit-latency-us = <145>; min-residency-us = <720>; }; - cluster_sleep_l: cluster-sleep-l { + cpu_off_l: cpu-off-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010002>; local-timer-stop; @@ -210,7 +274,7 @@ exit-latency-us = <155>; min-residency-us = <860>; }; - cluster_sleep_b: cluster-sleep-b { + cpu_off_b: cpu-off-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010002>; local-timer-stop; @@ -534,8 +598,7 @@ "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; - clock-names = "clk13m"; + clocks = <&clk13m>; }; pwrap: pwrap@10026000 { @@ -578,6 +641,8 @@ compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; #clock-cells = <1>; + /* power domain dependency not upstreamed */ + status = "fail"; }; uart0: serial@11002000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts index 3348ba69ff6c..2d5e8f371b6d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts @@ -10,6 +10,16 @@ compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195"; }; +&audio_codec { + compatible = "realtek,rt5682i"; + realtek,btndet-delay = <16>; +}; + +&sound { + compatible = "mediatek,mt8195_mt6359_rt1019_rt5682"; + model = "mt8195_r1019_5682"; +}; + &ts_10 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts index 4669e9d917f8..2586c32ce6e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -10,6 +10,11 @@ compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195"; }; +&audio_codec { + compatible = "realtek,rt5682i"; + realtek,btndet-delay = <16>; +}; + &pio_default { pins-low-power-hdmi-disable { pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, @@ -30,6 +35,11 @@ }; }; +&sound { + compatible = "mediatek,mt8195_mt6359_rt1019_rt5682"; + model = "mt8195_r1019_5682"; +}; + &ts_10 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts index 5021edd02f7c..f54f9477b99d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts @@ -11,6 +11,11 @@ "google,tomato", "mediatek,mt8195"; }; +&audio_codec { + compatible = "realtek,rt5682s"; + realtek,amic-delay-ms = <250>; +}; + &pio_default { pins-low-power-hdmi-disable { pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, @@ -31,6 +36,11 @@ }; }; +&sound { + compatible = "mediatek,mt8195_mt6359_rt1019_rt5682"; + model = "m8195_r1019_5682s"; +}; + &ts_10 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 560103e29017..56749cfe7c33 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -26,6 +26,12 @@ stdout-path = "serial0:115200n8"; }; + dmic-codec { + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <50>; + }; + memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x80000000>; @@ -117,9 +123,49 @@ reg = <0 0x50000000 0 0x2900000>; no-map; }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xd80000>; + no-map; + }; + + afe_mem: memory@60d80000 { + compatible = "shared-dma-pool"; + reg = <0 0x60d80000 0 0x100000>; + no-map; + }; + + adsp_device_mem: memory@60e80000 { + compatible = "shared-dma-pool"; + reg = <0 0x60e80000 0 0x280000>; + no-map; + }; + }; + + spk_amplifier: rt1019p { + compatible = "realtek,rt1019p"; + label = "rt1019p"; + pinctrl-names = "default"; + pinctrl-0 = <&rt1019p_pins_default>; + sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; }; }; +&adsp { + status = "okay"; + + memory-region = <&adsp_device_mem>, <&adsp_mem>; +}; + +&afe { + status = "okay"; + + mediatek,etdm-in2-cowork-source = <2>; + mediatek,etdm-out2-cowork-source = <0>; + memory-region = <&afe_mem>; +}; + &dp_intf0 { status = "okay"; @@ -225,6 +271,17 @@ clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; + + audio_codec: codec@1a { + /* Realtek RT5682i or RT5682s, sharing the same configuration */ + reg = <0x1a>; + interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; + realtek,jd-src = <1>; + + AVDD-supply = <&mt6359_vio18_ldo_reg>; + MICVDD-supply = <&pp3300_z2>; + VBAT-supply = <&pp3300_z5>; + }; }; &i2c3 { @@ -329,6 +386,11 @@ vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; }; +&mt6359codec { + mediatek,dmic-mode = <1>; /* one-wire */ + mediatek,mic-type-0 = <2>; /* DMIC */ +}; + /* for CPU-L */ &mt6359_vcore_buck_reg { regulator-always-on; @@ -536,6 +598,34 @@ "AP_SPI_FLASH_MOSI", "AP_SPI_FLASH_MISO"; + aud_pins_default: audio-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, + <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, + <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, + <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, + <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, + <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, + <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>, + <PINMUX_GPIO0__FUNC_TDMIN_MCK>, + <PINMUX_GPIO1__FUNC_TDMIN_DI>, + <PINMUX_GPIO2__FUNC_TDMIN_LRCK>, + <PINMUX_GPIO3__FUNC_TDMIN_BCK>, + <PINMUX_GPIO60__FUNC_I2SO2_D0>, + <PINMUX_GPIO49__FUNC_I2SIN_D0>, + <PINMUX_GPIO50__FUNC_I2SO1_MCK>, + <PINMUX_GPIO51__FUNC_I2SO1_BCK>, + <PINMUX_GPIO52__FUNC_I2SO1_WS>, + <PINMUX_GPIO53__FUNC_I2SO1_D0>; + }; + + pins-hp-jack-int-odl { + pinmux = <PINMUX_GPIO89__FUNC_GPIO89>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + cr50_int: cr50-irq-default-pins { pins-gsc-ap-int-odl { pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; @@ -777,6 +867,13 @@ }; }; + rt1019p_pins_default: rt1019p-default-pins { + pins-amp-sdb { + pinmux = <PINMUX_GPIO100__FUNC_GPIO100>; + output-low; + }; + }; + scp_pins: scp-default-pins { pins-vreq { pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; @@ -850,6 +947,18 @@ }; }; +&sound { + status = "okay"; + + mediatek,adsp = <&adsp>; + mediatek,dai-link = + "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE", + "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE", + "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; +}; + &spi0 { status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index dec85d254838..b2485ddfd33b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -78,6 +78,23 @@ }; }; +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 80000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + ethernet_phy0: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + &i2c6 { clock-frequency = <400000>; pinctrl-0 = <&i2c6_pins>; @@ -258,6 +275,66 @@ }; &pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, + <PINMUX_GPIO78__FUNC_GBE_TXD2>, + <PINMUX_GPIO79__FUNC_GBE_TXD1>, + <PINMUX_GPIO80__FUNC_GBE_TXD0>; + drive-strength = <MTK_DRIVE_8mA>; + }; + pins-cc { + pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, + <PINMUX_GPIO88__FUNC_GBE_TXEN>, + <PINMUX_GPIO87__FUNC_GBE_RXDV>, + <PINMUX_GPIO86__FUNC_GBE_RXC>; + drive-strength = <MTK_DRIVE_8mA>; + }; + pins-rxd { + pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, + <PINMUX_GPIO82__FUNC_GBE_RXD2>, + <PINMUX_GPIO83__FUNC_GBE_RXD1>, + <PINMUX_GPIO84__FUNC_GBE_RXD0>; + }; + pins-mdio { + pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, + <PINMUX_GPIO90__FUNC_GBE_MDIO>; + input-enable; + }; + pins-power { + pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, + <PINMUX_GPIO92__FUNC_GPIO92>; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, + <PINMUX_GPIO78__FUNC_GPIO78>, + <PINMUX_GPIO79__FUNC_GPIO79>, + <PINMUX_GPIO80__FUNC_GPIO80>; + }; + pins-cc { + pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, + <PINMUX_GPIO88__FUNC_GPIO88>, + <PINMUX_GPIO87__FUNC_GPIO87>, + <PINMUX_GPIO86__FUNC_GPIO86>; + }; + pins-rxd { + pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, + <PINMUX_GPIO82__FUNC_GPIO82>, + <PINMUX_GPIO83__FUNC_GPIO83>, + <PINMUX_GPIO84__FUNC_GPIO84>; + }; + pins-mdio { + pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, + <PINMUX_GPIO90__FUNC_GPIO90>; + input-disable; + bias-disable; + }; + }; + gpio_keys_pins: gpio-keys-pins { pins { pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c10cfeb1214d..8f1264d5290b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -38,7 +38,13 @@ performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <308>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -51,7 +57,13 @@ performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <308>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -64,7 +76,13 @@ performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <308>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -77,7 +95,13 @@ performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <308>; - cpu-idle-states = <&cpu_off_l &cluster_off_l>; + cpu-idle-states = <&cpu_ret_l &cpu_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -90,7 +114,13 @@ performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&cpu_off_b &cluster_off_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -103,7 +133,13 @@ performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&cpu_off_b &cluster_off_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -116,7 +152,13 @@ performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&cpu_off_b &cluster_off_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -129,7 +171,13 @@ performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&cpu_off_b &cluster_off_b>; + cpu-idle-states = <&cpu_ret_b &cpu_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -151,22 +199,20 @@ core3 { cpu = <&cpu3>; }; - }; - cluster1 { - core0 { + core4 { cpu = <&cpu4>; }; - core1 { + core5 { cpu = <&cpu5>; }; - core2 { + core6 { cpu = <&cpu6>; }; - core3 { + core7 { cpu = <&cpu7>; }; }; @@ -175,7 +221,7 @@ idle-states { entry-method = "psci"; - cpu_off_l: cpu-off-l { + cpu_ret_l: cpu-retention-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; @@ -184,7 +230,7 @@ min-residency-us = <580>; }; - cpu_off_b: cpu-off-b { + cpu_ret_b: cpu-retention-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; @@ -193,7 +239,7 @@ min-residency-us = <740>; }; - cluster_off_l: cluster-off-l { + cpu_off_l: cpu-off-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010002>; local-timer-stop; @@ -202,7 +248,7 @@ min-residency-us = <840>; }; - cluster_off_b: cluster-off-b { + cpu_off_b: cpu-off-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010002>; local-timer-stop; @@ -215,18 +261,28 @@ l2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; }; }; @@ -248,6 +304,15 @@ status = "disabled"; }; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; @@ -687,8 +752,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt8195-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8195-wdt"; mediatek,disable-extrst; reg = <0 0x10007000 0 0x100>; #reset-cells = <1>; @@ -705,7 +769,7 @@ "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&topckgen CLK_TOP_CLK26M_D2>; + clocks = <&clk13m>; }; pwrap: pwrap@10024000 { @@ -1046,6 +1110,98 @@ status = "disabled"; }; + eth: ethernet@11021000 { + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg = <0 0x11021000 0 0x4000>; + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal", + "mac_cg"; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg = <&infracfg_ao>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + snps,clk-csr = <0>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; + }; + xhci0: usb@11200000 { compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; @@ -1258,9 +1414,9 @@ clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, <&clk26m>, - <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, <&clk26m>, - <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, /* Designer has connect pcie1 with peri_mem_p0 clock */ <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; clock-names = "pl_250m", "tl_26m", "tl_96m", @@ -1380,6 +1536,12 @@ dp_calibration: dp-data@1ac { reg = <0x1ac 0x10>; }; + lvts_efuse_data1: lvts1-calib@1bc { + reg = <0x1bc 0x14>; + }; + lvts_efuse_data2: lvts2-calib@1d0 { + reg = <0x1d0 0x38>; + }; }; u3phy2: t-phy@11c40000 { @@ -1549,6 +1711,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x11e30000 0xe00>; + power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; status = "disabled"; u2port1: usb-phy@0 { @@ -2139,6 +2302,66 @@ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; }; + jpgdec-master { + compatible = "mediatek,mt8195-jpgdec"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + jpgdec@1a040000 { + compatible = "mediatek,mt8195-jpgdec-hw"; + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_JPGDEC>; + clock-names = "jpgdec"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + jpgdec@1a050000 { + compatible = "mediatek,mt8195-jpgdec-hw"; + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_JPGDEC_C1>; + clock-names = "jpgdec"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + + jpgdec@1b040000 { + compatible = "mediatek,mt8195-jpgdec-hw"; + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ + iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; + clock-names = "jpgdec"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; + }; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>; @@ -2152,6 +2375,46 @@ #clock-cells = <1>; }; + + jpgenc-master { + compatible = "mediatek,mt8195-jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + jpgenc@1a030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1a030000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + jpgenc@1b030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1b030000 0 0x10000>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + larb20: larb@1b010000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1b010000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index d1b67c82d761..9cbd6dd8f671 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -202,7 +202,7 @@ #clock-cells = <1>; }; - toprgu: toprgu@10007000 { + watchdog@10007000 { compatible = "mediatek,mt8516-wdt", "mediatek,mt6589-wdt"; reg = <0 0x10007000 0 0x1000>; @@ -229,7 +229,6 @@ compatible = "mediatek,mt8516-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl>; - pins-are-numbered; gpio-controller; #gpio-cells = <2>; interrupt-controller; |