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authorLars Povlsen <lars.povlsen@microchip.com>2020-08-24 22:30:09 +0200
committerLars Povlsen <lars.povlsen@microchip.com>2020-09-16 11:38:20 +0200
commitba4d1c074fd7e5f5d1a5b025b510fd542fc04da5 (patch)
tree3e85429c2297b331ea17ad8534adcbaf84ffec6e /arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
parent08ee16e95492f41d69df3b7fbd942d35dfece6a9 (diff)
arm64: dts: sparx5: Add spi-nor support
This add spi-nor device nodes to the Sparx5 reference boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-6-lars.povlsen@microchip.com
Diffstat (limited to 'arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi')
-rw-r--r--arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 18a535a04368..f37b478d6534 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -38,6 +38,38 @@
};
};
+&spi0 {
+ status = "okay";
+ spi@0 {
+ compatible = "spi-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>; /* CS0 */
+ spi-flash@9 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0x9>; /* SPI */
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+ spi@0 {
+ compatible = "spi-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>; /* CS0 */
+ spi-flash@9 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0x9>; /* SPI */
+ };
+ };
+};
+
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",