diff options
| author | Robert Marko <robert.marko@sartura.hr> | 2023-02-21 11:50:38 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-05-17 14:13:31 +0200 |
| commit | a34ebb17546d209cbb0b9b2c94303f25749557d7 (patch) | |
| tree | f9532c85c3d03514b5a307e4f0f41c897cea1afc /arch/arm64/boot/dts/microchip | |
| parent | 70be83708c925b3f72c508e4756e48ad2330c830 (diff) | |
arm64: dts: microchip: sparx5: correct CPU address-cells
There is no reason for CPU node #address-cells to be set at 2, so lets
change them to 1 and update the reg property accordingly.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Link: https://lore.kernel.org/r/20230221105039.316819-2-robert.marko@sartura.hr
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/microchip')
| -rw-r--r-- | arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index ed6f57ce38f7..4996499cc738 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -24,7 +24,7 @@ }; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { @@ -39,14 +39,14 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x0>; + reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x1>; + reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; |