diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-04-22 00:31:55 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-05-17 14:12:03 +0200 |
| commit | f217d94fc632fece2a41030c2eebc4ed34a48b2a (patch) | |
| tree | dfaf8523c065ae3bb890fb6082eac33fe7bff8e4 /arch/arm64/boot/dts/microchip | |
| parent | 4c84cced9304303ed1c73e35277891249e3cc2cd (diff) | |
arm64: dts: microchip: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:
sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property
Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/microchip')
| -rw-r--r-- | arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 0367a00a269b..6f7651b06478 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -52,6 +52,8 @@ }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; |