diff options
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2018-12-13 13:14:30 -0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-02-07 19:03:57 +0100 |
| commit | 351648d0cc6d32b38f3e08c143bf637dc934997c (patch) | |
| tree | 36e35b9cf109ebbc4ba3388840d1ce9107c2e032 /arch/arm64/boot/dts/nvidia/tegra194.dtsi | |
| parent | dfd3cb6feb73a38777a18fe5b0a91670978f8b4b (diff) | |
arm64: tegra: Support 200 MHz for SDMMC on Tegra194
Change the SDMMC clock source to support a maximum frequency of 200 MHz
on Tegra194.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra194.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index ae9e593e149e..560c1b695825 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -346,6 +346,10 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC4>; clock-names = "sdhci"; + assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, + <&bpmp TEGRA194_CLK_PLLC4>; + assigned-clock-parents = + <&bpmp TEGRA194_CLK_PLLC4>; resets = <&bpmp TEGRA194_RESET_SDMMC4>; reset-names = "sdhci"; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; |