arm64: tegra: Add display support on Tegra194

Tegra194 contains a display architecture very similar to that found on
the Tegra186. One notable exception is that DSI is no longer a supported
output. Instead there are four display controllers and four SORs (with a
DPAUX associated to each of them) that can drive HDMI or DP.

Signed-off-by: Thierry Reding <treding@nvidia.com>

1 files changed, 335 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c2091bb16546..0e6d89c557b1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/tegra186-hsp.h>
 #include <dt-bindings/reset/tegra194-reset.h>
+#include <dt-bindings/power/tegra194-powergate.h>
 
 / {
 	compatible = "nvidia,tegra194";
@@ -418,6 +419,340 @@
 			      <0x0c3a0000 0x10000>;
 			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
 		};
+
+		host1x@13e00000 {
+			compatible = "nvidia,tegra194-host1x", "simple-bus";
+			reg = <0x13e00000 0x10000>,
+			      <0x13e10000 0x10000>;
+			reg-names = "hypervisor", "vm";
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bpmp TEGRA194_CLK_HOST1X>;
+			clock-names = "host1x";
+			resets = <&bpmp TEGRA194_RESET_HOST1X>;
+			reset-names = "host1x";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0x15000000 0x15000000 0x01000000>;
+
+			display-hub@15200000 {
+				compatible = "nvidia,tegra194-display", "simple-bus";
+				resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
+					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
+					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
+					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
+					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
+					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
+					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
+				reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
+					      "wgrp3", "wgrp4", "wgrp5";
+				clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
+					 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
+				clock-names = "disp", "hub";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				ranges = <0x15200000 0x15200000 0x40000>;
+
+				display@15200000 {
+					compatible = "nvidia,tegra194-dc";
+					reg = <0x15200000 0x10000>;
+					interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
+					clock-names = "dc";
+					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
+					reset-names = "dc";
+
+					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+					nvidia,head = <0>;
+				};
+
+				display@15210000 {
+					compatible = "nvidia,tegra194-dc";
+					reg = <0x15210000 0x10000>;
+					interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
+					clock-names = "dc";
+					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
+					reset-names = "dc";
+
+					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
+
+					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+					nvidia,head = <1>;
+				};
+
+				display@15220000 {
+					compatible = "nvidia,tegra194-dc";
+					reg = <0x15220000 0x10000>;
+					interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
+					clock-names = "dc";
+					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
+					reset-names = "dc";
+
+					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+
+					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+					nvidia,head = <2>;
+				};
+
+				display@15230000 {
+					compatible = "nvidia,tegra194-dc";
+					reg = <0x15230000 0x10000>;
+					interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
+					clock-names = "dc";
+					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
+					reset-names = "dc";
+
+					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+
+					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+					nvidia,head = <3>;
+				};
+			};
+
+			dpaux0: dpaux@155c0000 {
+				compatible = "nvidia,tegra194-dpaux";
+				reg = <0x155c0000 0x10000>;
+				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_DPAUX>,
+					 <&bpmp TEGRA194_CLK_PLLDP>;
+				clock-names = "dpaux", "parent";
+				resets = <&bpmp TEGRA194_RESET_DPAUX>;
+				reset-names = "dpaux";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+				state_dpaux0_aux: pinmux-aux {
+					groups = "dpaux-io";
+					function = "aux";
+				};
+
+				state_dpaux0_i2c: pinmux-i2c {
+					groups = "dpaux-io";
+					function = "i2c";
+				};
+
+				state_dpaux0_off: pinmux-off {
+					groups = "dpaux-io";
+					function = "off";
+				};
+
+				i2c-bus {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			dpaux1: dpaux@155d0000 {
+				compatible = "nvidia,tegra194-dpaux";
+				reg = <0x155d0000 0x10000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
+					 <&bpmp TEGRA194_CLK_PLLDP>;
+				clock-names = "dpaux", "parent";
+				resets = <&bpmp TEGRA194_RESET_DPAUX1>;
+				reset-names = "dpaux";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+				state_dpaux1_aux: pinmux-aux {
+					groups = "dpaux-io";
+					function = "aux";
+				};
+
+				state_dpaux1_i2c: pinmux-i2c {
+					groups = "dpaux-io";
+					function = "i2c";
+				};
+
+				state_dpaux1_off: pinmux-off {
+					groups = "dpaux-io";
+					function = "off";
+				};
+
+				i2c-bus {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			dpaux2: dpaux@155e0000 {
+				compatible = "nvidia,tegra194-dpaux";
+				reg = <0x155e0000 0x10000>;
+				interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
+					 <&bpmp TEGRA194_CLK_PLLDP>;
+				clock-names = "dpaux", "parent";
+				resets = <&bpmp TEGRA194_RESET_DPAUX2>;
+				reset-names = "dpaux";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+				state_dpaux2_aux: pinmux-aux {
+					groups = "dpaux-io";
+					function = "aux";
+				};
+
+				state_dpaux2_i2c: pinmux-i2c {
+					groups = "dpaux-io";
+					function = "i2c";
+				};
+
+				state_dpaux2_off: pinmux-off {
+					groups = "dpaux-io";
+					function = "off";
+				};
+
+				i2c-bus {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			dpaux3: dpaux@155f0000 {
+				compatible = "nvidia,tegra194-dpaux";
+				reg = <0x155f0000 0x10000>;
+				interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
+					 <&bpmp TEGRA194_CLK_PLLDP>;
+				clock-names = "dpaux", "parent";
+				resets = <&bpmp TEGRA194_RESET_DPAUX3>;
+				reset-names = "dpaux";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+				state_dpaux3_aux: pinmux-aux {
+					groups = "dpaux-io";
+					function = "aux";
+				};
+
+				state_dpaux3_i2c: pinmux-i2c {
+					groups = "dpaux-io";
+					function = "i2c";
+				};
+
+				state_dpaux3_off: pinmux-off {
+					groups = "dpaux-io";
+					function = "off";
+				};
+
+				i2c-bus {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			sor0: sor@15b00000 {
+				compatible = "nvidia,tegra194-sor";
+				reg = <0x15b00000 0x40000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
+					 <&bpmp TEGRA194_CLK_SOR0_OUT>,
+					 <&bpmp TEGRA194_CLK_PLLD>,
+					 <&bpmp TEGRA194_CLK_PLLDP>,
+					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
+					 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
+				clock-names = "sor", "out", "parent", "dp", "safe",
+					      "pad";
+				resets = <&bpmp TEGRA194_RESET_SOR0>;
+				reset-names = "sor";
+				pinctrl-0 = <&state_dpaux0_aux>;
+				pinctrl-1 = <&state_dpaux0_i2c>;
+				pinctrl-2 = <&state_dpaux0_off>;
+				pinctrl-names = "aux", "i2c", "off";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+				nvidia,interface = <0>;
+			};
+
+			sor1: sor@15b40000 {
+				compatible = "nvidia,tegra194-sor";
+				reg = <0x155c0000 0x40000>;
+				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
+					 <&bpmp TEGRA194_CLK_SOR1_OUT>,
+					 <&bpmp TEGRA194_CLK_PLLD2>,
+					 <&bpmp TEGRA194_CLK_PLLDP>,
+					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
+					 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
+				clock-names = "sor", "out", "parent", "dp", "safe",
+					      "pad";
+				resets = <&bpmp TEGRA194_RESET_SOR1>;
+				reset-names = "sor";
+				pinctrl-0 = <&state_dpaux1_aux>;
+				pinctrl-1 = <&state_dpaux1_i2c>;
+				pinctrl-2 = <&state_dpaux1_off>;
+				pinctrl-names = "aux", "i2c", "off";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+				nvidia,interface = <1>;
+			};
+
+			sor2: sor@15b80000 {
+				compatible = "nvidia,tegra194-sor";
+				reg = <0x15b80000 0x40000>;
+				interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
+					 <&bpmp TEGRA194_CLK_SOR2_OUT>,
+					 <&bpmp TEGRA194_CLK_PLLD3>,
+					 <&bpmp TEGRA194_CLK_PLLDP>,
+					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
+					 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
+				clock-names = "sor", "out", "parent", "dp", "safe",
+					      "pad";
+				resets = <&bpmp TEGRA194_RESET_SOR2>;
+				reset-names = "sor";
+				pinctrl-0 = <&state_dpaux2_aux>;
+				pinctrl-1 = <&state_dpaux2_i2c>;
+				pinctrl-2 = <&state_dpaux2_off>;
+				pinctrl-names = "aux", "i2c", "off";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+				nvidia,interface = <2>;
+			};
+
+			sor3: sor@15bc0000 {
+				compatible = "nvidia,tegra194-sor";
+				reg = <0x15bc0000 0x40000>;
+				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
+					 <&bpmp TEGRA194_CLK_SOR3_OUT>,
+					 <&bpmp TEGRA194_CLK_PLLD4>,
+					 <&bpmp TEGRA194_CLK_PLLDP>,
+					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
+					 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
+				clock-names = "sor", "out", "parent", "dp", "safe",
+					      "pad";
+				resets = <&bpmp TEGRA194_RESET_SOR3>;
+				reset-names = "sor";
+				pinctrl-0 = <&state_dpaux3_aux>;
+				pinctrl-1 = <&state_dpaux3_i2c>;
+				pinctrl-2 = <&state_dpaux3_off>;
+				pinctrl-names = "aux", "i2c", "off";
+				status = "disabled";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+				nvidia,interface = <3>;
+			};
+		};
 	};
 
 	sysram@40000000 {