diff options
| author | Vidya Sagar <vidyas@nvidia.com> | 2022-10-25 23:55:08 +0530 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2022-11-21 13:30:13 +0100 |
| commit | 47a2f35d9ea76d92aa2385671f527b75aa9dfe45 (patch) | |
| tree | d575b90f3f586f79f51ec60b119025809ca66230 /arch/arm64/boot/dts/nvidia | |
| parent | b8f44643d68cdf64cebc42d276b5e4094f98a01f (diff) | |
arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
Fix the starting address of the non-prefetchable aperture of PCIe C3
controller.
Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 22dc93a326f0..aa278f565eea 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2350,7 +2350,7 @@ bus-range = <0x0 0xff>; ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, |