diff options
| author | Gautham Srinivasan <gauthams@nvidia.com> | 2023-07-21 16:10:50 +0000 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2023-07-27 16:42:12 +0200 |
| commit | bb9667d8187b58f1524a3ce203a0ddd7b107347a (patch) | |
| tree | 5b1340189999a502a1136586fc81388d3936c321 /arch/arm64/boot/dts/nvidia | |
| parent | 96ff27cecbc9dec9858786228c351341372b482f (diff) | |
arm64: tegra: Add SPI device tree nodes for Tegra234
Create the device tree nodes for the SPI1, SPI2 and SPI3 controllers
found on Tegra234.
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra234.dtsi | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f067326739c6..95524e5bce82 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -818,6 +818,44 @@ dma-names = "rx", "tx"; }; + spi@3210000 { + compatible = "nvidia,tegra210-spi"; + reg = <0x0 0x03210000 0x0 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_SPI1>; + assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "spi"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + resets = <&bpmp TEGRA234_RESET_SPI1>; + reset-names = "spi"; + dmas = <&gpcdma 15>, <&gpcdma 15>; + dma-names = "rx", "tx"; + dma-coherent; + status = "disabled"; + }; + + spi@3230000 { + compatible = "nvidia,tegra210-spi"; + reg = <0x0 0x03230000 0x0 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_SPI3>; + clock-names = "spi"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_SPI3>; + reset-names = "spi"; + dmas = <&gpcdma 17>, <&gpcdma 17>; + dma-names = "rx", "tx"; + dma-coherent; + status = "disabled"; + }; + spi@3270000 { compatible = "nvidia,tegra234-qspi"; reg = <0x0 0x3270000 0x0 0x1000>; @@ -1743,6 +1781,25 @@ dma-names = "rx", "tx"; }; + spi@c260000 { + compatible = "nvidia,tegra210-spi"; + reg = <0x0 0x0c260000 0x0 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_SPI2>; + clock-names = "spi"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_SPI2>; + reset-names = "spi"; + dmas = <&gpcdma 19>, <&gpcdma 19>; + dma-names = "rx", "tx"; + dma-coherent; + status = "disabled"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x0c2a0000 0x0 0x10000>; |