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authorSameer Pujar <spujar@nvidia.com>2023-06-29 10:42:17 +0530
committerThierry Reding <treding@nvidia.com>2023-07-13 17:13:25 +0200
commitdc6d5d85ed3a3fe566314f388bce4c71a26b1677 (patch)
treec4e00412703a51bbd0050858b08f8008da306547 /arch/arm64/boot/dts/nvidia
parente483fe34adab3197558b7284044c1b26f5ede20e (diff)
arm64: tegra: Update AHUB clock parent and rate
I2S data sanity test failures are seen at lower AHUB clock rates on Tegra234. The Tegra194 uses the same clock relationship for AHUB and it is likely that similar issues would be seen. Thus update the AHUB clock parent and rates here as well for Tegra194, Tegra186 and Tegra210. Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components") Cc: stable@vger.kernel.org Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi3
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi3
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi3
3 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 7e4c496fd91c..2b3bb5d0af17 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -135,7 +135,8 @@
clocks = <&bpmp TEGRA186_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
+ assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
+ assigned-clock-rates = <81600000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x02900800 0x02900800 0x11800>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 154fc8c0eb6d..33f92b77cd9d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -231,7 +231,8 @@
clocks = <&bpmp TEGRA194_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
+ assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
+ assigned-clock-rates = <81600000>;
status = "disabled";
#address-cells = <2>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 617583ff2736..e7b4e3013964 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1386,7 +1386,8 @@
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "ahub";
assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
+ assigned-clock-rates = <81600000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702d0000 0x702d0000 0x0000e400>;