diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-08-25 00:19:44 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-11-14 11:03:45 -0600 |
| commit | 5e2af1902d7409fdd60d425690141e643eff583c (patch) | |
| tree | 39d4c162d9538c4c13141bbeb147a386fa95a9b5 /arch/arm64/boot/dts/qcom/ipq8074.dtsi | |
| parent | 5de106ec1ea9b6106a0263cb2741ebfd7c39e820 (diff) | |
arm64: dts: qcom: ipq8074: switch USB QMP PHY to new style of bindings
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230824211952.1397699-9-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/ipq8074.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/ipq8074.dtsi | 76 |
1 files changed, 32 insertions, 44 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5d05819f356d..3d4ff7476320 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -125,32 +125,26 @@ ssphy_1: phy@58000 { compatible = "qcom,ipq8074-qmp-usb3-phy"; - reg = <0x00058000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x00058000 0x1000>; clocks = <&gcc GCC_USB1_AUX_CLK>, - <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "aux", "cfg_ahb", "ref"; + <&xo>, + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB1_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3phy_1_cc_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; resets = <&gcc GCC_USB1_PHY_BCR>, - <&gcc GCC_USB3PHY_1_PHY_BCR>; - reset-names = "phy","common"; - status = "disabled"; + <&gcc GCC_USB3PHY_1_PHY_BCR>; + reset-names = "phy", + "phy_phy"; - usb1_ssphy: phy@58200 { - reg = <0x00058200 0x130>, /* Tx */ - <0x00058400 0x200>, /* Rx */ - <0x00058800 0x1f8>, /* PCS */ - <0x00058600 0x044>; /* PCS misc */ - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB1_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3phy_1_cc_pipe_clk"; - }; + status = "disabled"; }; qusb_phy_1: phy@59000 { @@ -168,32 +162,26 @@ ssphy_0: phy@78000 { compatible = "qcom,ipq8074-qmp-usb3-phy"; - reg = <0x00078000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x00078000 0x1000>; clocks = <&gcc GCC_USB0_AUX_CLK>, - <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "aux", "cfg_ahb", "ref"; + <&xo>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3phy_0_cc_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; resets = <&gcc GCC_USB0_PHY_BCR>, - <&gcc GCC_USB3PHY_0_PHY_BCR>; - reset-names = "phy","common"; - status = "disabled"; + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; - usb0_ssphy: phy@78200 { - reg = <0x00078200 0x130>, /* Tx */ - <0x00078400 0x200>, /* Rx */ - <0x00078800 0x1f8>, /* PCS */ - <0x00078600 0x044>; /* PCS misc */ - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3phy_0_cc_pipe_clk"; - }; + status = "disabled"; }; qusb_phy_0: phy@79000 { @@ -628,7 +616,7 @@ compatible = "snps,dwc3"; reg = <0x8a00000 0xcd00>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - phys = <&qusb_phy_0>, <&usb0_ssphy>; + phys = <&qusb_phy_0>, <&ssphy_0>; phy-names = "usb2-phy", "usb3-phy"; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; @@ -670,7 +658,7 @@ compatible = "snps,dwc3"; reg = <0x8c00000 0xcd00>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - phys = <&qusb_phy_1>, <&usb1_ssphy>; + phys = <&qusb_phy_1>, <&ssphy_1>; phy-names = "usb2-phy", "usb3-phy"; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; |