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authorRobert Marko <robimarko@gmail.com>2023-04-26 20:56:47 +0200
committerBjorn Andersson <andersson@kernel.org>2023-05-24 19:39:05 -0700
commitcb0c14dae63fae037db41174fc95a59dea0ecf77 (patch)
tree8f1303276c16dc8ab72c7476ad8f627f790e4154 /arch/arm64/boot/dts/qcom/ipq8074.dtsi
parent93fe463652504bba298a68b56334729cdf92c0c3 (diff)
arm64: dts: qcom: ipq8074: Add QUP5 SPI node
Add node to support the QUP5 SPI controller inside of IPQ8074. Some devices use this bus in order to manage external switches. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230426185647.180166-1-robimarko@gmail.com
Diffstat (limited to 'arch/arm64/boot/dts/qcom/ipq8074.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/ipq8074.dtsi14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 0bde1303bb9d..74ce93e9bd67 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -533,6 +533,20 @@
status = "disabled";
};
+ blsp1_spi5: spi@78b9000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b9000 0x600>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
blsp1_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;