diff options
| author | Stephan Gerhold <stephan@gerhold.net> | 2023-05-29 14:46:59 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-05-29 14:37:01 -0700 |
| commit | c310ca82e229124e7b373125d82ea8fdbf2f9f81 (patch) | |
| tree | f3ce31a6a84caee9ed9c8447c27e9d59f27639f3 /arch/arm64/boot/dts/qcom/msm8916.dtsi | |
| parent | 41e22c2ff38eaea777f1158071539e659aa7980d (diff) | |
arm64: dts: qcom: msm8916/39: Rename &blsp1_uartN -> &blsp_uartN
For some reason the BLSP UART controllers have a label with a number
behind blsp (&blsp1_uartN) while I2C/SPI are named without (&blsp_i2cN).
This is confusing, especially for proper node ordering in board DTs.
Right now all board DTs are ordered as if the number behind blsp does
not exist (&blsp_i2cN comes before &blsp1_uartN). Strictly speaking
correct ordering would be the other way around ('1' comes before '_').
End this confusion by giving the UART controllers consistent labels.
There is just one BLSP on MSM8916/39 so the number is redundant.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-2-bec0f5fb46fb@gerhold.net
Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8916.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index a363be2d48e9..10670cfd2a6e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1598,7 +1598,7 @@ qcom,ee = <0>; }; - blsp1_uart1: serial@78af000 { + blsp_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; @@ -1607,12 +1607,12 @@ dmas = <&blsp_dma 0>, <&blsp_dma 1>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; status = "disabled"; }; - blsp1_uart2: serial@78b0000 { + blsp_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b0000 0x200>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; @@ -1621,8 +1621,8 @@ dmas = <&blsp_dma 2>, <&blsp_dma 3>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; status = "disabled"; }; |