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authorRichard Acayan <mailingradian@gmail.com>2023-08-01 21:15:50 -0400
committerBjorn Andersson <andersson@kernel.org>2023-08-03 20:47:09 -0700
commit8cd5597a9b18b890c743f50cfc5237fc74c6b9a0 (patch)
tree661299feb05fd1c4a7ad3cb42d29b5987d478424 /arch/arm64/boot/dts/qcom/sdm670.dtsi
parent41c1855232ed277e74daedbecac8d328b6c2ceb8 (diff)
arm64: dts: qcom: sdm670: add osm l3
Add the interconnect node for L3 cache on SDM670. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230802011548.387519-8-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sdm670.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sdm670.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index a1c207c0266d..45f9633d2d2c 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1354,5 +1354,15 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <3>;
};
+
+ osm_l3: interconnect@17d41000 {
+ compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
+ reg = <0 0x17d41000 0 0x1400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
};
};