diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2023-02-15 12:33:52 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-03-14 19:30:47 -0700 |
| commit | 1b0911fe3edb0895c43db4c19729b3c300028189 (patch) | |
| tree | cde8fdc3b7c7a6b0fda0d14fcad30aed7a60f930 /arch/arm64/boot/dts/qcom/sm8550.dtsi | |
| parent | afa34380d973491e87ab01d13c387528e2e1c476 (diff) | |
arm64: dts: qcom: sm8550: Supply clock from cpufreq node to CPUs
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.
So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-5-manivannan.sadhasivam@linaro.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8550.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 8992d6580bf3..71051fb4172b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -68,6 +68,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; @@ -91,6 +92,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; @@ -110,6 +112,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; @@ -129,6 +132,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x300>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; @@ -148,6 +152,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; @@ -167,6 +172,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; @@ -186,6 +192,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; @@ -205,6 +212,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; @@ -3323,6 +3331,7 @@ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; pmu@24091000 { |